The Work  / Interlude III
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Mini-EE · Interlude III · after Chapter 12 · three 14–15 minute lessons

Most of the job is proving you were right.

Twelve chapters have taught you to design circuits. That was the right thing to teach and it is not what most of the work is. On a modern chip project, creating the design — the schematic, the RTL, the part a degree prepares you for — is roughly a quarter of the engineering hours, and in some teams less than a tenth. The rest goes into establishing that the thing you drew actually does what you said. This interlude is about that other three quarters: who sells the tools for it, why it is the part that would not get cheaper, and what the machines that write code have and have not changed about it.

Assumes
Chapters 1–12, Interludes I and II
Per lesson
14–15 min
Figures current as of
September 2026
Next
Nothing — this closes the course
01

Where the hours actually go

15 minutes · the arithmetic of a project’s engineering time
Recall From chapter 12: phase margin turned out to be a property of what, exactly — and not of what? show answer

Chapter 12 closed on a relocation. Stability looked like a property of the amplifier, and it was not; it belonged to the loop the amplifier was wired into. You had to move the property from the part you were looking at to the relationship it was sitting in.

This interlude does the same move one level up, to the job itself. You have spent twelve chapters learning to design. It is worth knowing, before you go looking for work, roughly what fraction of the work that is.

The misconception

“An electronics degree trains you to design circuits, and designing circuits is what the job is.” This is the natural reading of a curriculum. Every course, this one included, is organised around creating something: bias this stage, size that mirror, compensate this loop. The assessment is whether your design works. So the job must be a longer version of the assessment.

It is not, and the gap is not small. Take the two numbers the industry actually measures. Design engineers on integrated-circuit projects report spending about half their time on verification rather than design. And on a typical project there is roughly one verification engineer for every design engineer — in processor teams, five. Put those together and the share of a project’s engineering hours that goes into creating the design comes out at about a quarter. In a processor team, under a tenth. That is the bench.

Notice what kind of claim this is. It is not that design is unimportant — it is the part everything else is about. It is that the hours have moved, and they moved into establishing correctness.

Commit before you touch anything

On a typical integrated-circuit project — one verification engineer per design engineer, which is what the industry survey finds — what share of the total engineering hours goes into creating the design? Writing the RTL, drawing the schematic, sizing the devices.

Answer: C. Exactly 25.5%, on the survey’s own two numbers. The design engineer gives 51% of their time to design; there is one verification engineer alongside them giving none; so the design-authoring share of the pair’s hours is 0.51 / 2. Slide the ratio to 5 : 1 and it falls to 8.5% — about 41 minutes of an eight-hour day. Slide it to zero and the misconception becomes true again, which is the interesting part.

The arithmetic, in full

There is no modelling here worth hiding. Take one design engineer and r verification engineers. The design engineer spends a fraction s of their time designing. Verification engineers spend none. Then the share of the group’s hours spent creating the design is

design share = s ÷ (1 + r). With the 2024 survey’s s = 0.51 and its typical r = 1, that is 25.5%. At r = 5, it is 8.5%. At r = 0 — a one-person analogue project, a board you are laying out yourself — it is 51%, and the misconception is correct.

That last case matters. The belief is not simply wrong; it is true in a particular regime and people carry it out of that regime without noticing. The regime where it holds is the one every student has direct experience of: you, alone, with a circuit. Add a verification team and it collapses fast. Set s = 0.51 and the design share drops below half at r = 0.02 — one verification engineer per fifty designers is already enough to tip it.

What moved, and when

The ratio was not always one to one. Across the surveys, demand for verification engineers grew at 10.3% a year between 2007 and 2016 while design engineers grew at 3.4%. That is the decade the inversion happened. Since 2016 the two have grown at similar rates — 3.0% against 2.4% — because the ratio had already arrived where it needed to be and teams now staff to it deliberately.

Meanwhile the thing all that effort is buying has been getting worse. The share of chip projects whose first silicon works, with no respin at all, was around 30% for most of the 2010s. In the 2024 survey it was 14% — the lowest in the twenty years the question has been asked. Three quarters of projects finished behind schedule, up from about two thirds historically. So this is not a story about a solved problem being over-resourced. It is a story about effort roughly keeping pace with a difficulty that keeps growing.

Why difficulty grows faster than size. Add one flip-flop to a design and you have added one component. You have also doubled the number of states the design can be in. Design effort scales with how much you have to write; verification effort scales with how much you have to rule out. Those are different functions of the same design, and only one of them is linear. This is the same reason chapter 12’s stability had to be checked over a whole frequency sweep rather than at one point.

The other reason is that the requirements multiplied. In 2024, 84% of chip projects contained at least one embedded processor, so hardware now has to be verified against software running on it. 95% contained two or more asynchronous clock domains, which brings a class of failure that cannot be reproduced in ordinary simulation at all. 83% included security features. 44% were built under a functional-safety standard, and those projects spent a median of a quarter to a half of their entire schedule on safety activity alone. None of that is circuit design. All of it is engineering, and somebody with your training does it.

In the wild

The job title you have never heard of. Search any large semiconductor company’s careers page for “design verification engineer” and then for “design engineer”. The first list is usually longer. It is the most common first job in the industry for someone with your degree, and almost no undergraduate course names it.

The bug that shipped. Intel’s FDIV bug in 1994 was five missing entries in a lookup table — a design error of trivial size that survived to silicon and cost about $475 million to recall. The modern verification industry is in a real sense the institutional memory of that quarter.

Your own experience of it. If you have ever built a circuit on a breadboard, you already know the ratio in miniature: twenty minutes wiring it, two hours with a meter working out why it does not do what you meant. Chip projects did not invent that ratio. They industrialised it.

Before you move on

Someone objects: “a quarter is just the average — plenty of engineers really do spend their day designing.” What is the honest response?

B. The 25.5% is a share of project hours, pooled over two roles, and the bench says so. The individual design engineer is not at 25% — they are at 51%, which is still only half. Both facts point the same way and neither needs the other. A overstates it: at r = 0 the design share is 51% and the original belief holds, which the bench lets you see. D is true but unhelpful without the numbers; the survey’s point is that the spread runs from about 1:1 to about 5:1, and the design share is a quarter to a twelfth across that whole range.
Bench 01 · where a project’s hours go —
● Locked until you commit a prediction above.
1.00
02.55
49 %
30 %45 %60 %
Hours creating the design—
Hours establishing it works—
Checking per hour of designing—
Designing, per 8-hour day—
creating the design establishing it works surveyed operating points
02

The tools, and who sells them

14 minutes · a $5.7 billion quarter, and the one category that is shrinking
Recall From Interlude II: for a 28 nm chip at ten million units, silicon was what share of the cost per die — and what dominated instead? show answer

Interlude II found that a chip mostly costs engineering, not silicon. Lesson 1 has now told you what that engineering is mostly doing. This lesson looks at what it is doing it with, because the tools are not incidental — you will spend more of your career driving them than drawing anything.

Three companies matter. Cadence and Synopsys are public and report quarterly; Siemens EDA is a segment inside Siemens Digital Industries Software and does not break out its revenue, which is worth saying plainly rather than filling in with an estimate. Between them they cover essentially every step of getting from an idea to a mask set. Cadence reported $1.584 billion for its second quarter of 2026 and guides to about $6.3 billion for the year. Synopsys reported $2.477 billion for its third fiscal quarter ending 31 July 2026 and guides to about $9.7 billion — though that figure now includes Ansys, acquired in July 2025, so it is not a like-for-like chip-tools number.

What the industry sells, by category

The useful view is not company by company but category by category, because SEMI’s ESD Alliance collects exactly that from public and private members and publishes it quarterly. The most recent report covers the first quarter of 2026 and was released in July. Total revenue: $5,747.8 million, up 12.7% on the year. It divides into five categories, and the division is the lesson.

Commit before you touch anything

Of the five categories — semiconductor IP, computer-aided engineering (simulation, verification, analysis), IC physical design and verification (place, route, signoff), PCB layout, and services — which one shrank when you compare the last four quarters with the four before?

Answer: C. On the four-quarter trailing measure, IC physical design and verification was −0.9% — the only category to fall. Computer-aided engineering grew 13.1% on the same measure, semiconductor IP 13.7%, services 11.9%. The single largest category in the chip-design-tool industry is not a tool at all: semiconductor IP, at 40.6% of the bill. The part that draws the layout is barely an eighth of it, and falling.

Two things that follow

The first is that you buy more design than you draw. Semiconductor IP — pre-made, pre-verified blocks: processor cores, memory controllers, PHYs, interface logic — is $2,332.5 million a quarter, more than every simulation and verification tool sold put together. A modern chip is mostly assembled from parts somebody else designed and proved, and your job is to integrate them and establish that the assembly works. That is the same finding as lesson 1 arriving by a completely different route.

The second is that layout automation is a solved-enough problem and verification is not. Place-and-route is genuinely hard engineering, but it is mature, competitive, and no longer where the growth is. Simulation, formal methods and analysis are, because the difficulty there scales with a state space rather than a die area. The money is following the same curve the headcount followed in lesson 1, about a decade later.

Where open source actually fits

You do not have to spend a fortune to touch any of this, and that is newer than you would think. The open flow — Yosys for synthesis, OpenROAD for place and route, OpenLane and its successor LibreLane wrapping them into a push-button RTL-to-GDSII flow, Magic and KLayout for layout, OpenSTA for timing, Verilator and cocotb for simulation and testbenches — is real, is used, and has produced fabricated silicon.

The boundary is sharp and it is worth knowing precisely where it falls. Open-source flows are production-capable on open process design kits: SkyWater 130 nm, GlobalFoundries 180 nm, IHP’s 130 nm SiGe. Above that, the constraint is not usually the tools — OpenROAD can be pointed at proprietary kits and at the ASAP7 predictive 7 nm kit for research — it is that advanced-node PDKs are not open and never will be. A foundry’s 3 nm kit is its crown jewels, released under an agreement that forbids exactly the openness the flow assumes. Signoff quality is the other gap: DRC, LVS, timing and power signoff in open tools is not yet what a foundry will accept for an advanced node.

So the honest summary: open source has made it possible for a student to tape out real silicon at a mature node, which was unthinkable in 2019 and is routine now. It has not displaced the commercial stack anywhere near the leading edge, and the reason is a licensing fact rather than a software one.

What the vendors employ. The companies reporting into the ESD Alliance survey employed 72,544 people worldwide in the first quarter of 2026, up 12.6% year on year. For scale, the whole of the United States employed about 98,200 electronics engineers in 2025. The tools industry is not a small appendage to chip design; it is comparable in size to the discipline it serves.
In the wild

Tiny Tapeout. A shuttle service that puts a few hundred small student and hobbyist designs onto one shared die using the open flow, for a few hundred dollars a slot. It exists because Interlude II’s mask-set arithmetic is brutal for one design and fine for three hundred sharing.

Verilator in places you would not expect. Verilator compiles Verilog to C++ and is fast enough that it is used in commercial pre-silicon flows alongside paid simulators, not merely as a free substitute. Open source competing on speed rather than on price is a different thing from open source competing on price.

The licence server. Ask any working chip engineer about tool licences and you will get a story. Seats are metered, expensive, and shared; a regression that needs forty simulator licences at 2 a.m. is a scheduling problem as much as an engineering one. This is the day-to-day form the $5.7 billion takes.

Before you move on

Semiconductor IP is the largest category and growing at 13.7%. What does that most directly tell you about the job?

B, and it agrees with lesson 1. A block you bought still has to be configured, connected, and proved correct in your context — the survey’s own note is that projects reusing pre-verified IP spend less of their time in verification, not none. A is wrong in a specific way: buying a block does not automate design, it relocates it to whoever sold you the block. C may be true separately but is not what this number shows. D is a fact about the vendors, not about your day.
Bench 02 · the tool bill, Q1 2026 —
● Locked until you commit a prediction above.
0 quarters
now+3 years+6 years
Total—
Largest slice—
Growing fastest—
Growing slowest—
growing shrinking projected
03

The machine, and the market

15 minutes · what AI has changed in the design loop, and what you would be hired to do
Recall From chapter 8: the virtual short between an op-amp’s inputs was not a law of the device. What was it a consequence of, and when does it fail? show answer

Chapter 8 taught a habit that is about to earn its keep. The virtual short looked like a property of an op-amp and was really a consequence of the open-loop gain being large. Push the circuit somewhere the gain is not large and the property evaporates. The lesson was: find the condition the behaviour depends on before you trust the behaviour.

Apply that to the claim you will hear most often about this industry right now.

Two things are true and they are different

The first is genuinely deployed and not marketing. Reinforcement learning has been doing design-space optimisation in production for years: Synopsys announced the first 100 commercial tape-outs using DSO.ai in February 2023, with STMicroelectronics reporting a threefold productivity uplift and SK hynix a die-size reduction of up to 5%; by that May the company said the tally was over 200. Cadence’s Cerebrus does the same job on its own flow. What these tools do is search — they turn hundreds of tool-parameter knobs, run the flow repeatedly, and keep what scores best. That is a real and large win, and note what it automates: not judgement, but a search a human was doing by hand, slowly, over months.

The second claim is that large language models can now write the design. Here you need chapter 8’s habit, because the headline numbers depend entirely on a condition that is usually left out.

The benchmark, and the condition. VerilogEval is the standard test: 156 Verilog problems, averaging about sixteen lines of code each. On its human-written split, GPT-4o scored 63% first-attempt in the 2025 revision; multi-agent systems now report 95.9%, 97.4% and 97.2%. Read alone, that says the problem is solved. But NVIDIA built a harder benchmark, CVDP, from realistic design and verification tasks, and the same class of models scored 34%, 29% and 23%. Same models. The condition the 97% depends on is that the problem is sixteen lines long.

That is not a reason to dismiss the tools. Sixteen-line modules are a real part of the work and getting them written fast is worth having. It is a reason to be exact about what has been bought, and there is a sharper point underneath.

Commit before you touch anything

A generator scores 97.2% first-attempt on the benchmark — the best published figure. You use it on a design of 500 modules. Of those 500, how many can you now skip verifying?

Answer: D. None. You must check all 500, because a pass rate tells you how many failed, never which. Identifying the 14 broken modules is exactly the act of verifying all 500. So a high pass rate reduces the time spent writing and the time spent fixing — it does not reduce the time spent checking, and lesson 1 established that checking is roughly three quarters of the job.

What a pass rate costs you downstream

The bench makes this concrete. Give each module an independent chance p of being right, let everything downstream — lint, simulation, formal, review — catch a fraction f of the broken ones, and the rest reach silicon. At the best published pass rate, 500 modules, and a catch rate of 90%, you get 14 broken modules, 1.4 of them escaping, and a 24.6% chance that first silicon works.

Compare that with the number lesson 1 gave you: the industry actually achieves 14%. A crude independence model landing within a factor of two of the measured figure is not proof of anything, but it does show the shape is right. Real modules are not independent and not equally hard; the bench names that as an assumption rather than hiding it.

Now run it the other way, which is the useful direction. Ask what catch rate you would need to reach the industry’s real 14% at each published generator score. At 97.2% you need to catch 86.0% of the failures. At GPT-4o’s 63% you need 98.9%. At CVDP’s 34% you need 99.4%. As the generator gets worse the checking has to get very close to perfect, very fast — which is precisely why the verification effort in lesson 1 did not fall when the tools improved. Generation and verification are not substitutes. Cheap generation raises the verification bar.

Where this is actually landing

The useful summary, as of September 2026: AI is deployed and valuable in search and optimisation (design-space exploration, place-and-route tuning), it is increasingly useful in drafting (RTL, testbenches, assertions, documentation) with a human checking everything, and it is being sold hard for autonomy, where the peer-reviewed evidence is thinner than the marketing. An ICCAD 2025 panel paper written jointly by academics and by engineers from IBM and Synopsys is titled, with some feeling, Revolution or Hype? — and its conclusion is that the answer depends on the task, the data and the constraints, which is the correct answer and an unsatisfying one.

So what would you actually be hired as

Numbers first, from the US Bureau of Labor Statistics, updated August 2026 with May 2025 wage data. The three occupations your degree points at look like this:

Computer hardware engineers $161,740
Median annual wage, May 2025 — the highest of any engineering occupation BLS tracks. Employment projected to grow 9% from 2025 to 2035, about 4,100 openings a year.
Electronics engineers, except computer $130,220
98,200 employed in 2025, growing just 4% to 2035 — barely above the 3% average for all occupations. Within it, semiconductor manufacturing pays the most at a median of $146,700.
Electrical engineers $120,630
199,700 employed, growing 10%. The fastest-growing of the three, and the one furthest from this course — power, grid and data-centre infrastructure rather than chips.

Read those honestly. Every one of them pays well above the $50,980 median for all US occupations. But the growth rates say something the enthusiasm does not: the branch of the field this course has taught is projected to grow at 4%, while the electrical-power side grows at 10%. Chip work pays better and is growing slower. Both facts are in the same table.

The skills that actually appear in entry-level chip postings follow directly from lessons 1 and 2, and mostly are not what an undergraduate course grades you on: SystemVerilog and UVM for building testbenches; assertions and enough formal method to use an automatic app; scripting in Python and Tcl, because every tool is driven by a script; version control and continuous integration, because a regression suite is software; and the ability to read somebody else’s block and work out what it promises. The circuit knowledge in this course is the foundation those sit on — you cannot debug what you do not understand — but it is the foundation, not the building.

In the wild

The interview question. A common first-round question for a verification role is not “design a circuit” but “here is a specification and a block — how would you convince yourself it is correct?” The expected answer names coverage, corner cases, and what you would formally prove rather than simulate.

What the survey says about talent. The 2024 study calls out a widening talent gap in design and verification engineering as one of its two headline industry challenges, alongside debug. That is a hiring signal, and it points at the verification side of the ratio.

The tools you can have today. Everything in lesson 2’s open flow installs on a laptop. You can write a small core, synthesise it with Yosys, place and route it with OpenROAD on SkyWater 130 nm, and simulate it with Verilator, this week, for nothing. Nobody could do that when the engineers now hiring you were students.

Before you move on

Why does a generator improving from 63% to 97.2% not cut the verification effort by a comparable amount?

B is the structural reason and it does not depend on how good the model gets. A is a separate and also true point — the same models drop to 34% on realistic tasks — but it is a claim about today’s scores, whereas B would still hold at 99.9%. C is false: formal adoption has been growing at 5.8% a year and automatic formal apps at 8.7%. D confuses a cultural fact with an arithmetic one.
Bench 03 · what a pass rate buys —
● Locked until you commit a prediction above.
97.2 %
20 %60 %100 %
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Modules to check—
Modules to fix—
Bugs reaching silicon—
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P(first silicon works) industry actual, 14% published pass rates

Every word this interlude introduced

Functional verification L1
Establishing that a design does what its specification says, before it is manufactured. Roughly three quarters of a modern chip project’s engineering hours, across both roles.
Design verification engineer L1
The role that does that work full time. About one per design engineer on a typical project, five per design engineer on processors. The most common first job in the industry for an electronics graduate.
First-silicon success L1
A project reaching production with no respin. Achieved by 14% of chip projects in 2024, the lowest figure in the twenty years the question has been surveyed.
Respin L1
Fixing a bug found in manufactured silicon and paying for a new mask set and run. Interlude II priced the mask set; this is what makes verification worth its headcount.
Clock-domain crossing L1
A signal passing between two asynchronous clocks, where metastability failures cannot be shown by ordinary RTL simulation. Present in 95% of chip designs, and the reason static CDC tools exist.
EDA L2
Electronic design automation — the software you design chips with. A $5.7 billion quarter in Q1 2026, dominated by Cadence, Synopsys and Siemens EDA.
Computer-aided engineering L2
The ESD Alliance category holding simulation, formal verification and analysis. $2,018.4 million in Q1 2026, growing 13.1% on the four-quarter measure.
Semiconductor IP L2
Pre-designed, pre-verified blocks licensed rather than drawn — cores, controllers, PHYs. The largest single category at 40.6% of the bill, which is why integration is so much of the job.
PDK L2
Process design kit — the models, rules and cell libraries a foundry gives you for one process. Open at 130 and 180 nm; confidential at every advanced node, which is the real limit on open-source flows.
RTL-to-GDSII flow L2
The full path from a register-transfer-level description to the polygons sent for masks. OpenLane and LibreLane are open implementations of it.
UVM L3
Universal Verification Methodology — the Accellera standard class library most SystemVerilog testbenches are built on. The single most-named skill in entry-level verification postings.
Design-space optimisation L3
Using reinforcement learning to search tool-parameter space for better power, performance and area. Shipping since 2023 and the least-disputed use of AI in the flow.
pass@1 L3
The share of benchmark problems a generator solves on its first attempt. Tells you how many outputs are wrong; never which ones, which is why it does not reduce verification.

Where this goes next

DONE

You have finished Mini-EE

Twelve chapters and three interludes, from a doped crystal to a compensated feedback loop, with every idea met on a bench that actually solved it. There is no chapter fifteen. The next circuit is one you choose.

NEXT

Build something and prove it works

Take the open flow from lesson 2, write a small design, and then do the harder half: write the testbench, find your own bugs, and notice how the ratio in lesson 1 shows up in your own hours.

About the figures. Nothing here is simulated physics. Every number is either a sourced figure or a stated modelling assumption, and the four assumptions are named below. Figures current as of September 2026. Lesson 1. All survey figures are from Harry D. Foster, 2024 Wilson Research Group IC/ASIC Functional Verification Trend Report, Siemens EDA, published February 2025 — a randomised, vendor-independent study with 597 eligible participants and a stated margin of error of ±4% at 95% confidence. From it: design engineers spent 51% of their time on design and 49% on verification in 2024; the mean peak verification-to-design headcount ratio is about one to one across most segments and five to one in processors; demand for verification engineers grew at a 10.3% CAGR between 2007 and 2016 against 3.4% for design engineers, and at 3.0% against 2.4% between 2016 and 2024; 14% of projects achieved first-silicon success, the lowest in twenty years; 75% finished behind schedule against about 66% historically; 84% contained an embedded processor, 95% two or more asynchronous clock domains, 83% security features, and 44% worked under a safety-critical standard with a median 25–50% of project time on safety activity. The 2020 and 2022 splits quoted (53/47 and 51/49) are the corresponding IC/ASIC reports for those years; note that the frequently-cited 56/44 figure is the FPGA study and is not comparable. Assumption 1: the bench treats verification engineers as spending 100% of their time on verification. The study’s own task breakdown for them — test planning, testbench development, running simulation, debug, other — is entirely verification work, so this is close, but it is an assumption and the design share would rise slightly without it. Assumption 2: “mean peak number of engineers” is used as a proxy for the ratio of engineer-hours. Peak headcount is not an integral over a project and the study publishes no hours integral; if verification headcount peaks more sharply than design headcount, the true design share is higher than the bench shows. The FDIV recall provision of $475 million is Intel’s own 1994 annual report. Lesson 2. All category and region figures are the SEMI ESD Alliance Electronic Design Market Data report for the first quarter of 2026, press release dated 13 July 2026: total $5,747.8 million, up 12.7%, four-quarter moving average up 10.3%; computer-aided engineering $2,018.4 million (+15.5% year on year, +13.1% four-quarter); IC physical design and verification $751.3 million (+8.3%, −0.9% four-quarter); PCB and MCM layout $419.2 million (+4.8%, +4.3%); semiconductor IP $2,332.5 million (+14.1%, +13.7%); services $226.4 million (+6.5%, +11.9%); Americas $2,433.8 million, Asia Pacific $2,264.4 million, EMEA $766.4 million, Japan $283.1 million (−9.9%, −12.4% four-quarter); headcount at reporting companies 72,544, up 12.6%. The five categories sum exactly to the reported total; the four regions sum to $5,747.7 million against a reported $5,747.8 million, a $0.1 million rounding difference which the bench carries rather than silently correcting. Vendor figures are the companies’ own releases: Cadence Q2 2026, revenue $1.584 billion and full-year guidance of $6.260–6.340 billion, announced 27 July 2026; Synopsys Q3 fiscal 2026 ending 31 July 2026, revenue $2.477 billion and full-year guidance of about $9.715 billion at the midpoint, announced 26 August 2026 — that figure includes Ansys and is not a like-for-like chip-tools comparison. Siemens EDA does not report segment revenue and no estimate is substituted for it here. Assumption 3: the forward projection compounds each category’s published trailing four-quarter growth rate. The ESD Alliance publishes no forecast; this is arithmetic on a trailing rate and nothing more, and it is least trustworthy exactly where it is most interesting, at the shrinking category. Open-source tool status is from the projects’ own documentation and the FOSSi Foundation’s LibreLane announcement of August 2025, which states the flow is proven for commercial tape-outs on SkyWater 130 nm with GlobalFoundries 180 nm support and IHP support arriving; the survey of the wider ecosystem is Chaves et al., From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs, Electronics 15(5), March 2026. The US electronics-engineer employment figure used for scale is BLS, below. Lesson 3. Deployment figures are vendor announcements and are labelled as such: Synopsys, AI-designed Chips Reach Scale with First 100 Commercial Tape-outs, 7 February 2023, including STMicroelectronics’ stated threefold productivity uplift and SK hynix’s stated die-size reduction of up to 5%, with the “well over 200” figure from the Q2 fiscal 2023 earnings call in May 2023. Benchmark figures are peer-reviewed or preprint: VerilogEval is Liu et al., ICCAD 2023, revised as Pinckney et al., Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation, ACM TODAES 2025, in which GPT-4o reaches 63% pass@1 on specification-to-RTL and Llama 3.1 405B reaches 57%; the 95.9%, 97.4% and 97.2% figures for MAGE, ChipAgents and ChipCraftBrain on VerilogEval-Human are as tabulated in the ChipCraftBrain preprint (arXiv 2604.19856, 2026), which also reports its own seven-run range of 96.15–98.72% and notes that the prior systems’ numbers are self-reported single runs — they are not independently replicated and should be read as claims, not measurements. CVDP is NVIDIA’s Comprehensive Verilog Design Problems (arXiv 2506.14074, 2025), reporting aggregate pass@1 of 34% for Claude 3.7 Sonnet, 29% for GPT-4.1 and 23% for Llama 3.1 405B, and lower still on its agentic split. The “16 lines” characterisation of VerilogEval problems is from the ChipCraftBrain preprint. Revolution or Hype? Seeking the Limits of Large Models in Hardware Design is Xu, Stok, Drechsler, Wang, Zhang and Markov, ICCAD 2025 (arXiv 2509.04905); its authors include engineers at IBM and Synopsys, which is why it is cited here rather than a purely academic critique. Assumption 4: the bench models module correctness as independent and identically distributed and treats any single escape as forcing a respin. Both are false in detail — modules differ enormously in difficulty, failures cluster, and some escapes are shipped as errata rather than respun. The model is included because it reproduces the measured 14% first-silicon rate to within a factor of two from published inputs, not because its assumptions are defensible; treat it as an argument about shape. Labour figures are the US Bureau of Labor Statistics Occupational Outlook Handbook, last modified 27 August 2026, carrying May 2025 wage data and 2025–35 projections: computer hardware engineers median $161,740 and +9%; electronics engineers except computer 98,200 employed, median $130,220, +4%, with a median of $146,700 within semiconductor manufacturing; electrical engineers 199,700 employed, median $120,630, +10%; all US occupations median $50,980 and +3%. Those are United States figures only and say nothing about any other labour market. What will date first: the benchmark scores, which move monthly and where today’s hard benchmark becomes next year’s saturated one; the vendor quarters and guidance; the ESD Alliance category figures, which are one quarter of a strong cycle; the specific AI products named; and the open-source flow’s node coverage, which advances. What is structural and will not need revising: that verification effort scales with a state space while design effort scales with what you write, so the two cannot stay in proportion; that a pass rate tells you how many outputs are wrong and never which, so cheap generation raises rather than lowers the verification bar; that advanced-node PDKs are confidential for commercial reasons no software project can route around; and that buying pre-verified IP relocates design work rather than removing it. If you are reading this well after September 2026, replace every number above and check whether those four still hold.