The Money  / Interlude II
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Mini-EE · Interlude II · after Chapter 10 · three 14–15 minute lessons

The silicon is the cheapest thing in the building.

Chapter 10 left you holding a question. You built a differential pair whose entire usefulness rests on two transistors being identical, and the closing callout said that matching is something you buy rather than something you draw. So: why is a matched pair on one die nearly free, while two matched resistors in your parts drawer are not? The answer turns out to explain the shape of the whole industry — who builds the factories, who never touched one, and where the money ends up.

Assumes
Chapters 1–10, Interlude I
Per lesson
14–15 min
Figures current as of
September 2026
Next
Chapter 11 · The CMOS Bench
01

Why the second transistor is free

15 minutes · what matching costs, on a die and off it
Recall From chapter 10: a 1% mismatch between the two halves of a differential pair produced how much input offset voltage? show answer

Chapter 10 spent six benches on a circuit that only works because two devices are the same. Not the same value — the same. The tanh split, the cancelling common mode, the offset that came out at 257 µV rather than tens of millivolts: every one of those depended on two transistors agreeing with each other to a fraction of a percent.

Now look at your parts drawer. Two resistors from the same bag agree to 1% if you paid for 1%, and 5% if you did not. Nobody sells you a bag of transistors that match. And yet the chapter said matching on a die is something you get almost for nothing, if you are willing to spend area on it. Both of those things are true, and the gap between them is enormous. This lesson measures it.

The misconception

“A chip costs what it costs because of the silicon.” It is the natural thing to think. Silicon is the exotic material, the wafer is the thing in the photographs, the fab is the expensive building. So the price must be the price of area. Once you believe that, matching looks like a straightforward purchase: better matching needs more area, more area costs more silicon, more silicon costs more money.

The arithmetic in this lesson kills the idea in one move. Matching on a die really does cost area, and the area really does grow fast. It is still about two thousand times cheaper than buying the same matching as discrete parts — and you can pay ten times more per wafer without denting that. Whatever you are paying for when you buy precision, it is not the silicon.

Commit before you touch anything

You need two components matched to 0.1%. Option one: two 0.1% discrete resistors from a distributor. Option two: two transistors laid out side by side on a 28 nm-class wafer, sized big enough to hit the same 0.1%. How much cheaper is the silicon?

Answer: D. Two 0.1% thin-film chip resistors are about 9.7 US cents at distributor prices. The two transistors need roughly 576 µm² each — a 24 µm square, which is enormous by digital standards — and at $3,000 a wafer that pair of squares costs $0.000049. A ratio of about 1,988. Drag the wafer price slider across every figure ever published for a 300 mm wafer and watch how little the answer moves.

One manufacturing event, not two

Here is the actual reason, and it has nothing to do with silicon being cheap. Two discrete resistors are two separate manufacturing events. Different substrates, possibly different lots, possibly different years, trimmed by different machines, sitting at different temperatures on your board. The difference between them is the difference between two independent draws from a wide distribution, and the only way to narrow it is to measure parts and throw away the ones that miss.

Two transistors on one die are one manufacturing event. Same wafer, same lot, same implant, same oxide growth, same anneal, same lithography exposure, microns apart, at the same temperature for the rest of their lives. Everything that would have made them differ has already been applied to both of them equally. What is left is only the local random part — individual dopant atoms landing where they land, the ragged edge of a printed line — and that part obeys a law.

Pelgrom’s law. For two nominally identical MOSFETs side by side, the standard deviation of the difference in their threshold voltages goes as σ(ΔVth) = AVT / √(WL). Bigger devices average over more randomness. The constant AVT, quoted in mV·µm, is a property of the process and is the number analogue designers ask a foundry for first. Marcel Pelgrom and colleagues, IEEE Journal of Solid-State Circuits, October 1989.

The consequence is a hard exchange rate. Because σ falls as the square root of area, halving your mismatch costs four times the area. There is no cleverness that gets around it; a common-centroid layout removes gradients, not randomness. Going from 0.1% to 0.01% is a hundredfold area increase — the 24 µm square becomes a 240 µm square, which is a visible speck on a die photograph and the reason precision analogue blocks look so absurdly large next to logic.

The exponent is not what integration changed

Put the two curves on the bench and something worth noticing appears. Silicon costs a hundred times more per decade of matching, because of that square-root law. The discrete parts do not follow the same rule at all. Going from 1% to 0.1% costs about 12× at the distributor, which is close to linear — that first decade is bought by sorting parts, and sorting scales with how many you throw away. Going from 0.1% to 0.01% costs about 142×, because at that point you have changed technology, changed vendor, and started paying for a measurement rather than a component.

So integration did not repeal the exponent. Over the range on the bench the silicon curve is the steeper of the two. What integration moved is the intercept, by three or four orders of magnitude. Making matching better is expensive everywhere. Having matching at all is what became free.

And this is where analogue stops scaling

Now do the experiment the industry actually ran. Take the same 0.1% pair from a 45 nm-class process at $3,000 a wafer to a 22 nm-class process at $20,000 a wafer. The matching coefficient improves by about 2.7×, so the area you need falls by about seven. The wafer costs 6.7× more. The two effects very nearly cancel, and the pair comes out at 0.94× its old cost. Fifteen years of scaling; no change.

Over those same years digital logic got several times denser per generation and a logic gate got cheaper every time. Analogue did not, because analogue does not buy transistors — it buys area, matching, headroom and noise, and none of those four scaled. That is the whole argument in one number, and lesson 3 is about what a company does when it finds itself holding that number.

In the wild

The instrumentation amplifier that is mostly a resistor network. An in-amp’s common-mode rejection is set by how well three resistor pairs track. Nobody builds one from loose parts. Vishay sells thin-film networks with ratio tolerance to 0.02% and tracking temperature coefficient of ±5 ppm/°C against ±25 ppm/°C absolute — the ratio is five times better than the values, for exactly the reason above: they are on one substrate, made in one event.

Laser trimming. If you cannot get matching from geometry, you buy it back afterwards by burning a notch in a thin-film resistor while watching a meter. It works, it is why a 0.01% part exists at all, and it is a per-part operation performed by a machine on a component — which is precisely the cost that integration deleted.

Why your op-amp datasheet has an offset drift spec. Chapter 10 showed VOS is proportional to VT and therefore to absolute temperature. Trimming at 25 °C cannot remove a slope. The part that gets you microvolts across temperature is a chopper, which measures its own offset thousands of times a second — buying matching with digital effort instead of area, because area got expensive and digital did not.

Before you move on

A colleague says on-die matching is cheap because silicon is cheap. What is the strongest single piece of evidence against that?

If silicon price were the explanation, the answer would be sensitive to it. Drive the wafer slider from $1,000 to $30,000 and the silicon cost moves by exactly 30× while the gap to the discrete parts is thousands of times — so the price of silicon cannot be doing the work. C is true and is the mechanism by which matching costs anything at all, but it argues the opposite way. D is true and is a separate reason to integrate. A is a real number that turns out not to matter here.
Bench 01 · what a matched pair costs —
● Locked until you commit a prediction above.
0.1 %
10 %0.1 %0.001 %
$3,000
$1,000$5,500$30,000
σ(ΔVth) needed—
Area, each device—
On-die pair—
Discrete pair—
on-die silicon discrete parts other AVT
02

Nobody who designs chips owns a factory

15 minutes · the fabless split, what a fab costs, and what a die costs
Recall From Interlude I: of the three curves that share the name “Moore’s Law”, which one was Moore himself writing about in 1965? show answer

Until the mid-1980s, a company that designed chips built them. Design and manufacturing were one business because a process and a design were developed against each other and could not be separated. Then in 1987 Morris Chang founded a company in Hsinchu that would manufacture other people’s designs and compete with none of them, and that single structural decision split the industry into two halves that have been diverging ever since.

The scale of the split now is easy to state and hard to absorb. In 2025 TSMC took $122.5 billion of revenue, which TrendForce puts at 69.9% of the entire global foundry market, up from 64.4% the year before. It ran 305 distinct process technologies and made 12,682 different products for 534 customers. It owns no product of its own.

Fabless
Designs chips, owns no factory, buys wafers. Nvidia, Apple, AMD, Qualcomm, Broadcom.
Foundry
Owns factories, makes other people’s designs, sells no chip of its own.
IDM
Integrated device manufacturer — does both, the old model. Intel, Samsung, Texas Instruments, Analog Devices.
OSAT
Outsourced assembly and test. Takes finished wafers, dices, packages and tests them. ASE is the largest.
NRE
Non-recurring engineering — everything you pay once before the first chip exists. Design, verification, IP licences, and the mask set.
Tape-out
The moment a design is handed to the foundry to be turned into masks. After it, changes cost a new mask set.

The reason the split happened, and the reason it will not un-happen, is the number at the bottom of a foundry’s cash-flow statement. TSMC spent $40.9 billion on capital equipment in 2025 against that $122.9 billion of revenue. In July 2026 it raised its guidance for the current year from $52–56 billion to $60–64 billion, which its CFO put at roughly 36% of sales. Nvidia, whose revenue in the quarter to July 2026 was $96.2 billion, spent $2.68 billion on property and equipment in the same period. That is 2.8%.

Part of that money buys machines from a company with no competitor. A current low-numerical-aperture EUV scanner runs around $200 million; the High-NA generation, ASML’s EXE:5200, is reported at about $400 million and there are fewer than a dozen in existence. When the Belgian research institute imec took delivery of one in March 2026, Reuters put the price at $400 million. There is one supplier on earth. That fact will matter again in lesson 3.

Commit before you touch anything

A 4 mm² microcontroller on a 28 nm process, sold ten million times. Of what it costs you to bring each one into existence, roughly what fraction is the silicon?

Answer: D, about 5%. A 300 mm wafer holds roughly 17,300 dies that size and nearly all of them work, so at $3,000 a wafer the silicon is 17½ cents. The design and mask set behind it are tens of millions of dollars, and ten million units is not many to spread that over: $3.31 per chip. The silicon does not overtake the fixed cost until about 191 million units. Set the bench to 28 nm and 4 mm², then drag the volume slider right until the dotted “silicon overtakes NRE” marker appears.

The only equation in this interlude

What a chip costs you, per chip, is two terms that behave in opposite ways:

  1. Silicon per good die. The wafer price divided by how many working dies come off it. Flat in volume — the millionth wafer costs what the first one did.
  2. NRE per die. Everything you paid before the first chip existed, divided by how many you sell. Falls as 1/volume, forever.

Working dies, not dies. A wafer is a fixed disc of about 70,700 mm² and you pay for all of it. Big dies fit worse and, much more importantly, catch more defects: at a defect density of about 0.11 per square centimetre, a 100 mm² die yields near 90% and an 800 mm² die yields 44%. Doubling die area does not double silicon cost — from 100 mm² upward, each doubling multiplies it by between 2.3 and 3.3.

The misconception is not always false — and where it is true is instructive. Take a reticle-sized 800 mm² accelerator on 3 nm at five million units. Fewer than twenty-nine good dies per wafer, so the silicon is around $628 a die and the NRE is around $76: silicon is 89% of the cost. For that one product category, in that one corner of the space, silicon really is the expensive part. Everywhere else on the bench it is a rounding error. A rule that holds only for the largest die anyone has ever made is not a rule about chips.

Nobody knows what a wafer costs

Here the sourcing runs into a wall, and the wall is the lesson. No foundry has ever published a wafer price. Every figure you have read is a supply-chain rumour reported by trade press, and they do not agree. For a 3 nm wafer the published estimates run from $18,000 to $27,000 — a spread of 50% on the single most-quoted number in chip economics.

NodeLow publishedHigh publishedSpread
28 nm$3,000$4,0001.3×
7 nm$9,500$9,500one figure only
5 nm$15,000$18,5001.2×
3 nm$18,000$27,0001.5×
2 nm$22,000$30,0001.4×

Design cost is worse. The most-cited figures come from International Business Strategies: $249 million at 7 nm, $449 million at 5 nm, $581 million at 3 nm, $725 million at 2 nm. But IBS’s own numbers move: its 2014 chart put 16/14 nm near $310 million and its 2018 chart put the same node at $106 million. Brian Bailey, writing in Semiconductor Engineering in 2023, applied that same discount forward and got roughly $280 million at 5 nm and $160 million at 7 nm; SemiAnalysis has said the IBS figures run 50 to 66% above what companies actually spend. The bench draws both readings as separate lines. They sit 1.4 to 1.6× apart on total cost per chip — which looks like a narrow gap only because the vertical axis spans six decades — and neither of them is wrong.

In the wild

Multi-project wafer shuttles. If a full mask set is the barrier, share one. Universities and startups buy a slot on a shuttle run — a few thousand dollars at 65 nm, tens of thousands at 28 nm — and get a few dozen dies back. It exists for exactly the reason this bench shows: at low volume the mask set, not the silicon, is what stops you.

Why the microcontroller in your project box is on an ancient node. Drag the bench to 28 nm and 4 mm², then to 3 nm and the same area. The silicon barely matters either way; the NRE goes up by an order of magnitude. There is no volume at which a $2 part earns back a $600 million design. Mature nodes are not a failure to keep up. They are the correct answer.

Chiplets. If yield collapses with die area, stop making big dies. Interlude I noted that Nvidia’s B200 reaches 208 billion transistors across two pieces of silicon rather than one. Set the bench to 800 mm², read the yield, then halve the area and read it again. That difference is the entire commercial case for advanced packaging, and it is why ASE exists.

Before you move on

You are choosing between 28 nm and 3 nm for a part you expect to sell 200,000 times. Which consideration dominates?

Two hundred thousand units is far below every crossover volume on the bench. Whatever you paid before the first chip existed is divided by a small number, so it swamps everything else — and the gap between the two nodes is roughly $50 million against $600 million. A, B and D are all real effects on the silicon term, and the silicon term is a few per cent of the answer at this volume.
Bench 02 · silicon against everything you paid first —
● Locked until you commit a prediction above.
100 mm²
4 mm²57 mm²800 mm²
10 M
10 k1 M100 M
Good dies per wafer—
Silicon per good die—
NRE per die—
Silicon’s share—
total per chip, low estimates total, high estimates silicon alone
03

Where the money actually lands

14 minutes · margin, capital, and why analogue never left its own fabs
Recall From lesson 1: to halve the mismatch between two on-die transistors, what happens to the area they need? show answer

Seven companies stand between a physics paper and a chip on your board. One sells the lithography machines. One owns the factories. One packages and tests what comes out. One does all three for its own products. One designs and owns nothing. Two design analogue parts and kept their own factories anyway. They all report their numbers every quarter, so you can simply look.

The obvious way to look is gross margin: of every dollar of revenue, how much is left after the direct cost of producing the thing. On that measure the ranking is not subtle. Nvidia, which owns no fab, reported 75.0% for the quarter ending July 2026. TSMC, which owns the fabs, reported 67.7%. ASE, which packages and tests, reported 21.0% across the group. Design captures more per dollar than manufacturing, and manufacturing captures more than assembly.

That is the story everyone tells, and it is incomplete in a way that this lesson’s bench makes visible in one click.

Commit before you touch anything

Gross margin ignores what a company spends rebuilding its factory. Subtract each firm’s capital spending, as a share of its own revenue, from its gross margin. TSMC starts second of the seven on gross margin. Where does it finish?

Answer: C. TSMC goes from 67.7% to 31.7% and drops from second to fifth. Nvidia barely moves, from 75.0% to 72.2%, because it spends 2.8% of revenue on equipment. Analog Devices lands second at 63.8%. ASE goes negative, to −19.0%, which is not an accounting error — its management said plainly that heavy investment may keep free cash flow negative for some time. Click through the three metrics on the bench and watch the order rearrange.

Margin is not the same as keeping the money

A foundry’s gross margin is calculated after the cost of running the fab, but the fab has to be rebuilt continuously to stay at the leading edge, and that spending sits somewhere else on the accounts. TSMC’s capital budget for 2026 is $60–64 billion, about 36% of sales. Intel’s is over $20 billion on a business running near $64 billion a year. ASE announced roughly $10.5 billion. Nvidia spent $2.68 billion in a quarter on $96.2 billion of revenue.

Subtract that and the spread across the seven widens from 54 points to 91 points. The ordering inverts around one axis: whoever has to rebuild the factory pays for the privilege of being essential. TSMC is not less profitable than Nvidia because it is worse at business. It is less profitable per dollar of revenue because the thing it sells requires it to buy $400 million machines from a company that has no competitor, forever, and Nvidia does not.

ASML is the interesting case. Fifty-four per cent gross margin puts it fifth of the seven — below TSMC, below both analogue firms. Move to the capital-adjusted view and it climbs to third, because its own capital spending is about 4.3% of revenue — though only just, at 49.7% against Texas Instruments’ 49.6%, which is well inside the error on a constructed capital-intensity figure and should be read as a tie. It sells the one machine nobody else can make, to customers who must buy it, and it does not need a fab to do it. That is what an unrepeatable position looks like on a balance sheet.

Which brings us back to the differential pair

Look at where Analog Devices and Texas Instruments sit. Both design analogue parts. Both own their own fabs, which by the logic of the fabless split they should have sold twenty years ago. Both sit near the top on both measures — ADI second, TI level with ASML for third — ahead of the leading-edge foundry.

Lesson 1 is why. Matching costs the same on a modern node as it did fifteen years ago, so there is nothing at the leading edge for an analogue part to go and get. Lesson 2 is the other half: analogue product lines sell in thousands of distinct part numbers at modest volume each, which is the worst possible place to be standing when NRE is the dominant term. So the analogue companies stayed on mature nodes, where the wafer is cheap and the mask set is cheap, and they kept their factories — because a mature fab is paid off, and a paid-off fab does not need $60 billion a year.

They are also buying something a foundry menu does not offer. Analogue processes carry thick gate oxides for parts that must survive 40 volts, precision poly resistors, metal-insulator-metal capacitors, trimmable elements, laser fuses. A leading-edge logic process has none of that, because logic does not need it. Owning the fab is how you own the option to add a process step for one product family.

CompanyGross marginCapex / revenueDifference
Nvidia — fabless75.0%2.8%72.2%
Analog Devices — analogue IDM67.3%3.5%63.8%
ASML — lithography54.0%4.3%49.7%
Texas Instruments — analogue IDM61.0%11.4%49.6%
TSMC — foundry67.7%36.0%31.7%
Intel — IDM40.4%31.3%9.1%
ASE — package and test21.0%40.0%−19.0%

One warning about reading that table. It is a single quarter of a boom, in an industry with a violent cycle. TSMC’s gross margin was 59.5% in the third quarter of 2025 and 67.7% in the second of 2026; Intel’s was 27.5% a year ago and 40.4% now. The ordering is structural and has held for years. The numbers are a photograph of one moment.

In the wild

The 741 is still for sale. A part designed in 1968, on a process nobody would call a node, still shipping because the tooling is long paid for and the design has earned back its NRE approximately a million times over. Every term in lesson 2’s equation has gone to zero except the silicon, and the silicon was never the expensive part.

TI building 300 mm fabs for analogue. Sherman, Texas and Lehi, Utah — large-scale 300 mm plants for parts that do not need a leading-edge node at all. The gain is not smaller transistors, it is more area per wafer for the same processing cost, which is precisely the currency lesson 1 says analogue trades in. TI has said it is nearing the end of a six-year elevated spending cycle and expects to spend $2–3 billion in 2026, down from about $4.6 billion in 2025.

The queue for packaging. An AI accelerator now needs three things at once: a wafer slot, an advanced packaging slot and a memory allocation. Any one without the other two ships nothing. That is why the least profitable link in the chain by gross margin is simultaneously the one raising capital spending fastest — scarcity is not the same thing as margin, and this quarter it is sitting in the packaging house.

Before you move on

Why do Analog Devices and Texas Instruments still own fabs when Nvidia, Apple and AMD do not?

All three halves of the argument point the same way. Lesson 1: the cost of a matched pair is flat across fifteen years of scaling, so the leading edge has nothing to sell them. Lesson 2: NRE dominates at modest volume, and mature nodes have cheap masks. And the process itself has to carry thick oxides, precision resistors and trimmable elements that a logic PDK does not include. The numbers agree — both firms clear the leading-edge foundry on margin net of capital.
Bench 03 · seven links, three ways to read them —
● Locked until you commit a prediction above.
40 %
−30 %25 %80 %
Highest—
Lowest—
Spread—
Above the line—
makes the tools owns factories analogue, owns factories designs only

Every word this interlude introduced

Pelgrom’s law L1
The mismatch between two nominally identical adjacent devices falls as the square root of their area: σ(ΔVth) = AVT/√(WL). Halving mismatch costs four times the area.
AVT L1
The matching coefficient of a process, in mV·µm. The first number an analogue designer asks a foundry for, and the one that has scaled worst.
Common-centroid layout L1
Splitting each of two devices into halves arranged in a cross, so a linear gradient across the die cancels. Removes gradients; does not touch the random part Pelgrom’s law describes.
Laser trimming L1
Cutting a thin-film resistor while measuring it, to reach a value geometry alone will not hold. A per-part operation, which is why it costs what it costs.
Fabless L2
A company that designs chips and owns no factory. Nvidia, Apple, AMD, Qualcomm, Broadcom.
Foundry L2
A company that owns factories and manufactures other companies’ designs, competing with none of them. TSMC took 69.9% of the market in 2025.
IDM L2
Integrated device manufacturer — designs and manufactures its own parts. Intel, Samsung, Texas Instruments, Analog Devices.
OSAT L2
Outsourced assembly and test. Dices, packages and tests finished wafers. ASE is the largest.
NRE L2
Non-recurring engineering — every cost incurred once, before the first chip exists. Design, verification, IP licensing and the mask set. Divided by volume, it is usually the dominant term.
Mask set L2
The full set of photomasks a design needs. Roughly $1 million at 28 nm and $10–20 million at 3 nm, paid before the first wafer starts.
Tape-out L2
Handing a finished design to the foundry for mask-making. After tape-out, a change costs a new mask set.
Gross die per wafer L2
How many dies of a given area fit on a wafer before yield. About 17,300 at 4 mm² and 64 at 800 mm² on a 300 mm wafer.
Murphy’s yield model L2
The standard estimate of the working fraction of dies from area and defect density. Yield falls fast with area: near 90% at 100 mm², about 44% at 800 mm².
Multi-project wafer L2
A shuttle run sharing one mask set between many designs, so a small team can get silicon without paying a full mask set.
Capital intensity L3
Capital spending as a share of revenue. TSMC guided about 36% for 2026; Nvidia’s was 2.8% in its July 2026 quarter.
High-NA EUV L3
ASML’s 0.55 numerical-aperture lithography platform. About $400 million a machine, fewer than a dozen in existence, one supplier on earth.

Where this goes next

CH 11

The CMOS Bench

Back to circuits, and straight into the process this interlude has been costing. The inverter, power, speed, and the scaling that made logic cheap while leaving the matched pair exactly where it was.

CH 12

The Loop Bench

The Miller effect, phase margin and stability — the compensation capacitor that eats die area on every op-amp ever made, which lesson 1 has now given you a price for.

About the figures. Nothing here is simulated. Every constant is either a sourced figure or a stated modelling assumption, and the three assumptions are named below. Figures current as of September 2026. Lesson 1. Pelgrom’s law is M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, Matching properties of MOS transistors, IEEE Journal of Solid-State Circuits 24(5), October 1989. The three AVT values are: 2.4 mV·µm at 45–50 nm, the figure used for the 50 nm worked examples in the Boise State thesis CMOS Characterization, Modeling, and Circuit Design in the Presence of Random Local Variation; below 1 mV·µm at 22 nm, stated as such in US patent 10,734,378 (Intel), of which the bench uses 0.9; and 4.8 mV·µm for 0.18 µm, which is derived rather than quoted — it is twice the 45 nm value, following the statement in arXiv:1606.05903 that between 180 nm and 45 nm feature size scaled by four while the matching coefficient improved only about twofold. Assumption 1: converting a threshold-voltage sigma into a percentage current mismatch needs a bias point, and the bench uses gm/ID = 10 V⁻¹, that is an overdrive of 200 mV. Change that and the on-die curve slides sideways; it does not change the shape or the conclusion. Discrete prices are RS Components UK catalogue listings read in September 2026, at each part’s best listed price break, converted at 1.35 USD/GBP: ±1% RS PRO 0603 thick film at £0.003 in reels of 5,000; ±0.1% Yageo RT0603 thin film at £0.036 from 1,000; ±0.01% TE RU73X thin film at £5.105 from 200. Those three are not a like-for-like family — three manufacturers, and the 0.01% part is 0805 rather than 0603 — so treat the discrete curve as the shape of distributor pricing, not as one product line. The resistor-network figures are Vishay’s Quick-Net data sheet; the thick-film against thin-film network comparison is Analog Devices, Ask The Applications Engineer–24: Resistance. Lesson 2. TSMC’s quarterly figures are its own SEC Form 6-K for the second quarter of 2026, filed 16 July 2026: revenue $40.20 billion, gross margin 67.7%, and 2 nm at 3% of wafer revenue, 3 nm 30%, 5 nm 33%, 7 nm 11%. The 2025 full-year figures, the 305 processes, 12,682 products and 534 customers, and the 2026 capital budget of $60–64 billion at roughly 36% of sales come from the same filing and the accompanying earnings call. Foundry market share is TrendForce, March 2026 (69.9% of 2025, $122.54 billion, against 64.4% in 2024) with Counterpoint Research putting TSMC at 73% of the pure-play market in the first and second quarters of 2026. EUV tool prices are trade reporting: about $200 million for current low-NA systems and about $400 million for the High-NA EXE:5200, the latter from Reuters via imec’s March 2026 delivery announcement. Wafer prices are the weakest data in this interlude and are presented as a band for that reason. No foundry publishes them. The low and high ends are, per node: 28 nm $3,000–$4,000 (Silicon Analysts, August 2026, compiled from TrendForce, Morgan Stanley and CSET); 7 nm $9,500 from the same compilation and no second published figure found, so that band is drawn as a single line; 5 nm $15,000 (implied by China Times’ statement, reported by Tom’s Hardware, that N2 is roughly twice N5) to $18,500; 3 nm $18,000 (China Times via OC3D) to $27,000 (supply-chain sources via TrendForce, October 2025); 2 nm $22,000 (the 10–20% increase reading) to $30,000 (the most widely reported figure). Design NRE: the high line is International Business Strategies as published — $51 million at 28 nm, $249 million at 7 nm, $449 million at 5 nm, $581 million at 3 nm, $725 million at 2 nm. The low line is that series multiplied by 0.633, a factor constructed for this bench: Brian Bailey, What Will That Chip Cost?, Semiconductor Engineering, October 2023, notes that IBS’s own 16/14 nm estimate fell from about $310 million in its 2014 chart to about $106 million in its 2018 chart, applies a comparable discount forward, and arrives at roughly $280 million at 5 nm and $160 million at 7 nm; 0.633 is the factor that reproduces both of those to within 2%. SemiAnalysis has separately put the IBS figures 50 to 66% high. Mask sets are $800 k–$1.5 million at 28 nm, $3–5 million at 7 nm, $5–8 million at 5 nm and $10–20 million at 3 nm (Silicon Analysts, August 2026) against IBS’s $5 million at 16/14 nm and $15 million at 7 nm — a threefold disagreement at 7 nm, which matters little because the mask is small beside the design. No published mask figure for 2 nm was found, so the bench carries the 3 nm band there, an error of under 4% of that node’s NRE. Assumption 2: gross die per wafer uses the standard 300 mm geometric approximation, and yield uses Murphy’s model at defect densities of 0.08 to 0.13 per cm² rising with node novelty. Those defect densities are the one set of numbers in this bench with no published source at all — they are conventional values, chosen to put a 100 mm² 3 nm die near 90% yield, and everything the bench says about yield inherits their uncertainty. Lesson 3. Every margin is from a company filing for its most recent reported quarter. TSMC 67.7% gross margin, Q2 2026 6-K. Nvidia 75.0% and $2.677 billion of property and equipment purchases against $96.221 billion revenue, Q2 fiscal 2027 ending 26 July 2026, Form 8-K. ASML 54.0% and 2026 capital expenditure of about €1.9 billion against €43–45 billion of guided sales, Q2 2026 press release and the 2025 Form 20-F. Intel 40.4% GAAP, Q2 2026 8-K, with 2026 capex guided above $20 billion. Texas Instruments 61% gross margin and 42% operating margin, Q2 2026, with 2026 capital expenditure guided at $2–3 billion in its Form 10-Q against about $4.6 billion spent in 2025. Analog Devices 67.3% GAAP gross margin, Q3 fiscal 2026 ending 1 August 2026, with capital expenditure of about $140 million implied by its stated $1.6 billion operating and $1.46 billion free cash flow. ASE 21.0% consolidated gross margin, Q2 2026 6-K, with announced 2026 capital expenditure of about $10.5 billion. Assumption 3: capital intensity is not reported on a common basis, so three of the seven are constructed and stated here rather than quoted: Intel at 31.3% is $20 billion against a $64 billion annualised run rate; Texas Instruments at 11.4% is the $2.5 billion midpoint against about $22 billion; ASE at 40.0% is $10.5 billion against about $26 billion implied by first-half actuals and third-quarter guidance. TSMC’s 36%, Nvidia’s 2.8%, ASML’s 4.3% and ADI’s 3.5% come straight from the filings. What will date first: every figure in lesson 3, which is a single quarter of an unusually strong cycle and will be replaced in weeks; the wafer prices and the 2026 capital budgets; the foundry market shares; and the High-NA machine count, which grows. What is structural and will not need revising: that mismatch scales as the square root of area and therefore costs four times the area to halve; that on-die matching is three to four orders of magnitude cheaper than the discrete equivalent; that fixed cost divided by volume dominates the cost of most chips; that yield collapses with die area; and that the ordering of the value chain inverts when you account for capital. If you are reading this well after September 2026, replace the numbers and check whether those five still hold.