Stability is not a property of the amplifier. It is a property of the loop.

Chapter 8 handed you an op-amp as a sealed unit: enormous open-loop gain, a virtual short at the input once feedback closes the loop, and no explanation of what was inside. Here is the inside, and you have already built both halves of it. The input stage is chapter 9 and chapter 10's mirror-loaded differential pair — two matched transistors, a current-mirror load, a single high-impedance output node. The second stage is a plain common-emitter gain stage, one transistor, driving the final output node.

Chain them and the gain multiplies: stage 1 turns a differential input into a voltage at its high-impedance node, A, with gain G_m1·R_A; stage 2 takes that voltage and delivers −G_m2·R_OUT more. The whole amplifier's open-loop DC gain is the product, and with realistic numbers it lands in the hundred-thousands to millions — comfortably enough to explain why chapter 8 called it "too high to use directly." This chapter's default lands at 133 dB, a touch under 4.5 million.

Node A is exactly the node chapters 9 and 10 built and warned you about: high impedance, because it is the output of a current source loaded by another current source, with nothing but two transistors' r_o pulling it toward either rail. High impedance at DC also means high impedance at any frequency an external capacitance can act on — and node A has one, however small, whether you put it there deliberately or not. That is where this chapter's whole subject begins.

The fix bench 1 needs is deliberate: put a capacitor, C_c, bridging node A directly to the output. It looks like it should simply add a little capacitance to node A. It does something far larger. Because the second stage inverts and amplifies, a small change in node A's voltage produces a much bigger, opposite change at the output — and C_c has to supply the current for both swings. From node A's point of view, C_c behaves as if it were roughly (1 + G_m2R_OUT) times larger than its physical value. With this chapter's numbers, that multiplier is in the thousands.

The consequence is exactly what a stability problem needs: node A's own pole crashes down in frequency (a huge effective capacitance on a high-impedance node makes for a very low corner), while the output node's pole — no longer starved of current by a struggling first stage — effectively moves higher. The two poles that were close together in bench 1 get pushed apart, one down and one up. This is pole splitting, and it is the entire mechanism behind "just add one capacitor."

The gain-bandwidth product that falls out of this is unusually clean. Once C_c is large enough to dominate node A, the frequency where the open-loop gain crosses 1 works out to G_m1/C_c — and nothing else. Not R_A, not R_OUT, not even G_m2. Two entirely different second stages, with wildly different gain and output resistance, give the same amplifier the same unity-gain frequency, so long as G_m1 and C_c are unchanged.

C_c was drawn as a one-way path from node A to the output, feeding the Miller effect that split the poles. It is not actually one-way. A capacitor conducts in both directions, and at high enough frequency C_c becomes a low-enough impedance that a signal can leak straight from node A to the output without going through the amplifying transistor at all — a feedforward path that bypasses the gain stage entirely.

That feedforward path fights the amplifier's own signal. At low frequency the amplified path dominates completely and C_c only does its intended job. At some higher frequency the two paths become comparable, and the transfer function picks up a real, solvable zero — on the right half of the complex plane, at roughly G_m2/C_c. A right-half-plane zero adds gain the way any zero does, but it subtracts phase the way a pole does — the worst of both worlds, and exactly what a stability margin does not need.

Look at where that zero sits: G_m2/C_c, against the unity-gain frequency from lesson 2, G_m1/C_c. If the two transconductances are similar, the zero and the unity-gain crossing land at almost the same frequency — the zero's phase damage arrives exactly where it hurts most. The fix does not touch C_c at all: bias the second stage at a noticeably higher current than the first, so G_m2 > G_m1, and the zero moves safely above the crossover with room to spare.

Everything so far has measured the amplifier open-loop — input to output, feedback disconnected. No one runs an op-amp that way. Close a feedback loop around it with a resistive divider feeding back a fraction β of the output to the input, and the quantity that actually decides stability is not the amplifier's own open-loop gain and phase — it is the loop gain, β·A(s), and specifically its phase at the frequency where its magnitude crosses 1.

Chapter 8 already introduced β from a different angle: it called 1/β the noise gain, and used it to explain the trade-off between how much a feedback network amplifies and how much bandwidth it delivers. That same β now decides something chapter 8 did not have the tools to show — how much of the open-loop phase margin the loop actually gets to keep. A large β (low closed-loop gain, heavy feedback, β close to 1) pushes the loop-gain crossing out toward the amplifier's own highest frequencies, where the most phase has already been lost to the second pole and the zero from lessons 2 and 3. A small β (high closed-loop gain, light feedback) crosses much lower, where those effects have barely begun.

This produces the sentence at the top of this chapter. Wire the exact same amplifier — same C_c, same bias currents, nothing changed inside the box — as a unity-gain buffer (β = 1, the heaviest feedback there is) and it may show a thin, workable phase margin or none at all. Wire it as a ×100 amplifier (β = 0.01) and the same box is rock stable. Nothing inside the amplifier changed. Only the loop did.

Chapter 8 measured slew rate from outside the box: drive a large step into a real op-amp and its output ramps at a fixed maximum rate, utterly unlike the smooth exponential a small-signal bandwidth would predict. It was presented there as a separate fact about the black box, alongside open-loop gain and offset, with no claim about where the number came from. It comes from here.

Drive the input hard enough — a big enough step — and chapter 10's differential pair does exactly what chapter 10's lesson 1 warned it would: it fully steers. All of the tail current, I_tail, is diverted to one side and none reaches the other. The transistor that used to supply a small signal current to node A is now supplying the entire tail, with nowhere else for it to go but into — or out of — the one capacitor sitting on that node: C_c, doing the dominant-pole job lesson 2 gave it.

A fixed current into a fixed capacitor gives a fixed rate of voltage change: dV/dt = I_tail/C_c. That is slew rate, in full. It has nothing to do with gain, bandwidth, or phase margin — it is a large-signal current-into-a-capacitor limit that only starts to matter once an input step is too big for the small-signal picture to apply at all, which is exactly why chapter 8 had to treat it as a separate specification rather than something the gain and bandwidth numbers already implied.

Five lessons have each moved one dial and watched one consequence. A real design has to move all of them at once, against a spec sheet. Bigger C_c buys phase margin (lesson 2) and moves the right-half-plane zero relatively closer if G_m2 is not raised to compensate (lesson 3), at the direct cost of slew rate (lesson 5) and gain-bandwidth (lesson 2, read the other way). A heavier output load capacitance, C_L, pulls the second, non-dominant pole down toward the crossover, eating back some of whatever margin C_c bought — which is the one variable this chapter has not yet turned a dial on.

None of this is free in a second sense, either. C_c is a real capacitor on the die, and a capacitor is area, and area on a wafer priced per square millimetre costs money regardless of what sits on it — Interlude II's whole argument, one sentence: a 30 pF compensation capacitor is not a rounding error next to a matched pair's tens of square micrometres; on many analogue processes it is the single largest passive component on the chip, competing for die area with everything else this course has built.

The practical version of every lesson so far is a single design sentence: pick the smallest C_c that delivers the phase margin the application needs, at the closed-loop gain the application will actually run at, against the load capacitance the application will actually drive — and check the resulting slew rate and bandwidth are still enough. Every term in that sentence has its own bench, three lessons back.