The CMOS Bench  / Chapter 11
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Mini-EE · Chapter 11 of 12 · six 13–15 minute lessons

A CMOS gate's power has nothing to do with how strong its transistors are.

Every digital chip you own is built from one part, repeated billions of times: an NMOS and a PMOS, drains tied together, gates tied together. No resistors, no bias current, no quiescent path to ground — the two chapter-7 devices you already built now do the whole job between them. The energy it costs to flip that pair once turns out not to depend on the very thing everyone reaches for first: how big you made the transistors.

Assumes
Chapters 1 to 10, Interlude II
Per lesson
13–15 min
The number
E = C·VDD2, independent of W
Next
Chapter 12 · The Loop Bench
01

Two chapter-7 devices, drains tied together

14 minutes · the complementary pair, and the point where both switches are half open
Recall From chapter 7: what does gm do as overdrive VOV rises, for a fixed drain current — and why does the intrinsic gain gmro fall as a result? show answer

Take one NMOS and one PMOS, both the square-law devices from chapter 7. Tie the two gates together — that is the input, Vin. Tie the two drains together — that is the output, Vout. Put the NMOS source at ground and the PMOS source at VDD. That is the whole circuit. It is called a CMOS inverter, and it is the single most repeated structure on any digital chip: every logic gate, every flip-flop, every SRAM cell is built from a handful of these wired together.

Read it as a pair of switches stacked between the rails. When Vin is near 0 V, the NMOS is off (VGS below its threshold) and the PMOS is hard on (its VSG is nearly the whole rail) — the output is pulled to VDD. When Vin is near VDD, the roles swap and the output is pulled to ground. In between, both devices are partway on at once, and that narrow region is where all the interesting physics of this chapter lives.

The point where the two switches trade places — where the transfer curve crosses Vout = Vin — is called the switching threshold, VM. It is not automatically at VDD/2: it lands wherever the NMOS's pull-down strength balances the PMOS's pull-up strength, and nothing so far has said those are equal.

Commit before you touch anything

Hold Vin at exactly VM, the point where the transfer curve crosses the diagonal. What state are the two transistors in?

Answer: B. At VM the output sits well clear of both rails, which means VDS on the NMOS and VSD on the PMOS are both comfortably above their own overdrives — the chapter-7 saturation condition, on both devices, at the same instant. That is exactly why this point matters: it is the one place on the curve where the inverter is not a switch at all but a two-transistor amplifier, with both devices contributing gain, and it is where the bench's badges will read SAT / SAT.

Why the crossing isn't automatically in the middle

Silicon does not give holes and electrons the same mobility — holes move at roughly 40% of the speed electrons do in the same field. A PMOS built with the same width and length as its NMOS partner is a substantially weaker pull-up. Left uncorrected, that drags VM up toward VDD: the NMOS wins the tug of war earlier, because it barely has to try. The standard fix is exactly the one real layouts use — draw the PMOS wider, by roughly the mobility ratio, until the two pull strengths match. It is why, if you have ever looked at a standard-cell layout, the PMOS row is visibly fatter than the NMOS row.

The inverter's default on this bench starts already corrected — the PMOS is sized 2.5× the NMOS's width to offset a 0.4× mobility ratio, which is why VM opens at the rail's midpoint. Slide either width control and watch it move off centre; that motion is the tug of war, made visible.

In the wild

The 7404 hex inverter, and every NOT gate since. Six of exactly this circuit in one package, unchanged in principle since the first CMOS logic families of the 1970s.

Standard-cell layout. Open any cell library's inverter and the PMOS transistor is drawn visibly wider than the NMOS — the mobility correction from this lesson, done in silicon rather than in a slider.

Schmitt-trigger inputs on microcontroller pins. Built from deliberately missized inverters, so the switching threshold on the way up differs from the way down — hysteresis, purchased with the same Wn/Wp knob this bench turns.

Before you move on

You make the PMOS much wider without touching the NMOS. What happens to VM?

A stronger PMOS holds the output high against a weaker challenge, so the NMOS needs more overdrive — a higher Vin — before it can drag the output down to meet it. The crossing moves toward VDD.
Bench 01 · the transfer curve —
● Locked until you commit a prediction above.
0.90 V
0 VVDD/2VDD
1.00×
0.25×1×4×
2.50×
0.6×2.5×10×
VM—
Vout here—
NMOS region—
PMOS region—
Small-signal gain here—
02

No resistors, and (almost) no current

13 minutes · the one moment the series path actually conducts
Recall From chapter 4: what is the difference between a circuit's DC bias point and the signal riding on it? show answer

Look again at the topology: NMOS and PMOS, drains tied together, no resistor anywhere. That is not an oversight — it is the entire reason CMOS displaced every logic family before it. At either rail, one device is hard on and the other is hard off, so the series path from VDD to ground is broken by a device sitting in cutoff. No current flows through an open switch, no matter how hard the closed one is pulling.

Compare that with chapter 6's push-pull stage, which needed a small standing bias current through both output devices just to avoid crossover distortion, or with chapter 5's resistor-biased common-emitter stage, which draws current from the supply continuously, whether or not anything is happening at the input. A CMOS gate sitting at either logic level draws nothing from its supply beyond the tiny leakage that lesson 5 takes up on its own.

The exception is the region this chapter has already found interesting for another reason: near VM, both devices are on at once, in saturation, in series. For a narrow slice of Vin around the crossing, there is a real path from rail to rail, and real current flows through it — drawn straight from the supply and dumped straight to ground, doing no useful work at all.

Commit before you touch anything

Sweep Vin slowly from 0 to VDD and watch the current drawn from the supply. What does the curve look like?

Answer: B. The bench shows a single spike, and it sits exactly at VM for a matched design — not a coincidence for this particular sizing, but not a law either; move Wn or Wp and watch the spike track VM as it shifts. Answer D is the trap: there are not two events, because the NMOS turning on and the PMOS turning off happen continuously, over the same sweep, and their product — not their sum — is what determines whether current flows.

Series, not parallel

Because there is no third path out of the shared drain node at DC, the NMOS's current and the PMOS's current are not independent quantities that happen to be measured separately — they are the same current, forced equal by Kirchhoff's current law the instant you tie the drains together. The bench's two current traces do not merely track each other closely; they sit exactly on top of one another, for the same reason chapter 10's two nearly-equal CMRR traces did not need rescaling to look convincing — here it is not two large numbers that happen to be close, it is one number measured twice.

This spike has a name in real design: short-circuit power, and it is a genuine third contributor to a chip's power budget alongside the dynamic and static components lessons 3 and 5 take up. It is worst when a gate's input is driven by a slow, lazy edge that lingers near VM — which is exactly why input buffers are built to sharpen edges before they reach anything that matters.

In the wild

Input buffer chains. A slow signal arriving at a chip's pin is deliberately passed through a chain of inverters before it reaches logic, specifically to shrink the time spent near VM and cut this spike down.

Bus contention. Two drivers fighting over one wire is this same rail-to-rail path, but external rather than internal — and it can draw enough current to damage a pad if it persists.

Why "don't leave inputs floating" is CMOS gospel. An undriven gate input can sit near VM indefinitely, drawing this current the whole time — the reason unused CMOS inputs are always tied high, low, or through a defined resistor, never left open.

Before you move on

Why does the NMOS current trace sit exactly on top of the PMOS current trace on this bench?

KCL at the shared drain node leaves no other path at DC. Sizing changes where the spike sits and how tall it is, but never separates the two traces — they are the same measurement.
Bench 02 · the short-circuit spike —
● Locked until you commit a prediction above.
0.90 V
0 VVDD/2VDD
1.00×
0.25×1×4×
2.50×
0.6×2.5×10×
IN here—
IP here—
Peak current, this sweep—
Vin at peak—
03

The energy per flip does not care how big you built the transistors

15 minutes · the misconception, and the charge-balance argument that kills it
Recall From chapter 7: doubling a FET's width at the same overdrive roughly doubles its drain current. What effect should that have on how fast it can charge a fixed capacitor? show answer

Every output node in a real chip drives something — the next gate's input, a length of wire, both. Model that as a capacitor, CL, sitting on the shared drain node. Every time the inverter flips, it either charges that capacitor from 0 to VDD through the PMOS, or discharges it from VDD to 0 through the NMOS. That charging and discharging is where a CMOS chip's dynamic power comes from — and where the widespread instinct that follows from lesson 1 and lesson 2 turns out to be wrong.

The instinct: a bigger transistor pushes more current, so surely it takes more energy to do its job. Chapter 7 already told you gm rises with overdrive and width — more current sounds like more everything. But energy is not current; it is current integrated over the time the job takes, and a bigger transistor finishes the job faster, in almost exact proportion. Whether those two effects cancel exactly is a question with a definite answer, and it is worth deriving before you look at the bench.

Take the charging edge. The charge delivered by the supply to raise the node from 0 to VDD is fixed by the capacitor alone — Q = CLVDD, regardless of the path that charge took to get there. The supply sits at a constant VDD throughout, so the energy it delivers is Q·VDD = CLVDD2. Nowhere in that derivation does the PMOS's width, its k, or its instantaneous current appear. They decide how long the charging takes. They cannot touch how much charge a fixed capacitor needs to reach a fixed voltage.

Commit before you touch anything — this is the chapter's misconception

You double every transistor's width, changing nothing else. What happens to the energy the supply delivers each time the output charges from 0 to VDD?

Answer: C. The bench's energy meter reads the same figure at every width setting, to four significant figures, while the delay meter moves by roughly the same factor the width moved by. A bigger transistor is a faster path to the same destination, not a cheaper or costlier one. This is the misconception this chapter exists to correct: a gate's dynamic power is set by its capacitance, its supply voltage, and how often it switches — never by how strong its transistors are.

Where the other half goes

The capacitor only ends up holding ½CLVDD2 of that energy — the rest is dissipated as heat in the PMOS while it charges. Then, on the next edge, the NMOS discharges the capacitor to ground and dissipates that stored ½CLVDD2 as heat too, delivering nothing back to the supply. A full 0→1→0 cycle therefore dissipates a full CLVDD2, split evenly between the two transistors, and none of it depends on which transistor did the dissipating or how wide it was built. Multiply by how often a node switches per second and you get the familiar figure, Pdynamic = α·CLVDD2·f, where α is the fraction of clock cycles that actually see a transition.

W buys speed. It does not buy energy. This is the sharpest single fact CMOS scaling has to offer: a chip can be made faster by widening its transistors at essentially no energy cost per operation, right up until the point — lesson 5 — where a different, unrelated law starts charging rent just for existing.

In the wild

Why "just make it bigger" is free, up to a point. Chip designers routinely upsize a critical gate to hit a timing target with no dynamic-power penalty — the reason timing closure and power closure are separate, largely independent jobs.

Dynamic voltage and frequency scaling (DVFS). Because Pdynamic goes as VDD2, dropping the supply a little saves far more power than dropping the clock the same fraction — the whole reason phones throttle voltage first.

Clock gating. Since α sits right there in the formula, stopping the clock to an idle block multiplies its dynamic power by zero — the single most effective power-saving trick in a modern SoC.

Before you move on

A designer replaces a gate's transistors with ones 4× wider to hit a timing deadline. What happens to that gate's dynamic energy per transition?

Bigger transistors finish faster, at essentially the same charge-balance cost. The bench's energy meter tracks CL and VDD2; it does not move when the width sliders do.
Bench 03 · energy per transition —
● Locked until you commit a prediction above.
1.00×
0.25×1×8×
20.0 fF
2 fF20 fF200 fF
Energy from supply, this charge edge—
Same, at 1× size (reference)—
Stored on CL (½CVDD2)—
Dissipated in PMOS, this edge—
04

What width actually buys

13 minutes · propagation delay, and the resistor lesson 3 left standing
Recall From chapter 7: in triode, a FET behaves like a voltage-controlled resistor. What made that true — what property of the I–V curve near VDS = 0? show answer

Lesson 3 showed what width does not buy. Here is what it does. During the discharge edge, the NMOS pulls the output from VDD toward ground by supplying current IN(Vout) to a capacitor of size CL. The rate of discharge is dVout/dt = −IN/CL. Since IN scales with W (chapter 7's square law, k ∝ W/L), doubling the NMOS's width roughly doubles the current available at every point on that curve, and the time to cross any fixed voltage span — conventionally, from VDD down to VDD/2, the propagation delay tpHL — falls by roughly the same factor.

Chapter 7's other result matters here too. So long as the discharge stays in saturation the whole way to VDD/2 — VOV comfortably below half the rail — the current is nearly constant across the transition, and the RC intuition of "resistor discharging a capacitor" is only a rough analogy: the actual device is a current source, not a resistor, until it drops into triode near the very end. If the swing crossed into triode earlier, the same voltage-controlled-resistor behaviour from chapter 7's lesson 6 would take over and the delay calculation would look more like an actual RC time constant. This bench's default sizing keeps the whole VDD→VDD/2 swing in saturation, so it behaves like the constant-current case.

Commit before you touch anything

You quadruple the NMOS width only, leaving the PMOS and CL unchanged. What happens to tpHL — the fall-time delay?

Answer: A. With the discharge staying in saturation, current and width move together almost exactly, so the delay very nearly quarters. It will not be a perfect quarter — the channel-length-modulation term is a small function of Vout, not of width, so it does not cancel out of the ratio quite as cleanly as the energy result in lesson 3 did. Answer D is a real effect in a full design (gate capacitance does grow with width, and it is exactly why an inverter driving another inverter, rather than a bare capacitor, eventually hits diminishing returns) but this bench models the load as a fixed external CL, so it is not visible here.
Sizing for a deadline is exactly this trade, run backwards. A designer with a timing budget and a known load capacitance picks the smallest width that gets there — not the biggest available, because lesson 3 said width was free but lesson 5 is about to say it is not quite free after all.

In the wild

Buffer chains driving long wires or big loads. A single gate cannot efficiently drive a large off-chip capacitance directly; a tapered chain of progressively wider inverters, each roughly 3–4× the last, gets there faster and at lower total energy than one giant gate.

Clock tree buffers. The literal biggest transistors on most digital chips exist for exactly this reason — driving a clock signal to thousands of destinations with minimum delay skew.

Why a "weak pull-up" I2C bus is slow. Deliberately undersized pull-up strength trades this chapter's speed for lower idle power — the same width knob, turned the other way on purpose.

Before you move on

Which of these speeds up a gate's propagation delay without changing its dynamic energy per transition at all?

Width moves delay without moving E = CLVDD2. VDD moves both, and moves the energy with a square — the sharpest single lever a designer has, which is why lesson 3's "In the wild" flagged DVFS.
Bench 04 · the discharge waveform —
● Locked until you commit a prediction above.
1.00×
0.25×1×8×
2.50×
0.6×2.5×20×
20.0 fF
2 fF20 fF200 fF
tpHL (fall)—
tpLH (rise)—
Average tp—
Implied max clock, 1/(2tp)—
05

The other curve

14 minutes · leakage, and why "one law" keeps failing this course
Recall Interlude I's whole point was that "Moore's Law" is at least three different curves people mistake for one. What were they? show answer

Everything so far has assumed a device below threshold conducts nothing. Real devices conduct a little even there — an exponentially small but never-zero subthreshold current, the same exponential shape as a diode's reverse leakage, governed by how many VT-widths of margin sit between VGS and VTH. Every "off" transistor on a chip leaks a little, all the time, whether or not the chip is doing anything — this is static power, and it is a genuinely separate curve from lesson 3's dynamic power, related to it only by both being called "power."

The two curves depend on almost disjoint sets of things. Dynamic power cares about CL, VDD2, and how often the gate switches — it vanishes at zero frequency. Static power cares about VTH and VDD, and it does not care about frequency at all: an idle chip still burns it, every second it is powered, doing nothing. The two curves cross at some frequency, above which dynamic power dominates and below which leakage does — and that crossing point is exactly where the low-power design conversation actually happens.

The lever that makes static power interesting is the same VTH this chapter has been sizing around since lesson 1. Lowering VTH gives every gate more overdrive at the same VDD, which lesson 4 says buys speed. But subthreshold current falls off exponentially in (VGS − VTH), so a lower VTH also means the "off" device is closer to "on," and leakage rises exponentially to match. There is no way to buy the first without paying the second.

Commit before you touch anything

You lower VTH by roughly 170 mV to speed up every gate on a chip, holding VDD and frequency fixed. What happens to the crossover frequency where static power equals dynamic power?

Answer: B. Roughly two decades of overdrive against an 85 mV/decade subthreshold slope is roughly two decades of leakage, and the crossing frequency moves with it — from a few tens of kilohertz to several megahertz on this bench's defaults. A chip idling below that new crossing burns more power doing nothing than it would have at the higher threshold; a chip that is never idle does not care.
This is the same "one law" trap Interlude I built a whole chapter around, back one level. There, three curves with different shapes got mistaken for a single "Moore's Law." Here, two curves with opposite dependence on frequency get mistaken for a single "power." A chip's actual power budget is the sum of two laws that do not even share their most important variable.

In the wild

Multi-threshold CMOS (HVT/SVT/LVT libraries). Real chips mix several threshold voltages on one die — low-VTH cells only on the timing-critical paths, high-VTH everywhere else — buying lesson 4's speed only where it is worth this lesson's leakage cost.

Power gating and sleep transistors. Cutting an idle block's supply rail entirely is the only way to beat subthreshold leakage outright, since lowering VDD alone still leaves a leakage path.

Why your phone's SoC has an idle power spec at all. That number is a direct read of the static curve, measured with the dynamic term forced to zero by clock gating.

Before you move on

A chip is running at a very high clock frequency, flat out. Which power term dominates?

Dynamic power rises linearly with frequency without bound (in this model); static power is a flat floor. High activity always eventually favours dynamic dominance.
Bench 05 · two curves, one crossing —
● Locked until you commit a prediction above.
0.420 V
0.25 V0.42 V0.55 V
100 MHz
1 kHz100 MHz10 GHz
Pdynamic here—
Pstatic here—
Crossover frequency f*—
Which dominates here—
06

What CMOS costs you that bipolar didn't

15 minutes · Pelgrom meets a real MOS bench, and three debts from chapters 9 and 10 come due
Recall From Interlude II: state Pelgrom's law, and what happens to the required area if you halve the mismatch you can tolerate. show answer

Interlude II introduced σ(ΔVth) = AVT/√(WL) and gave it three real, dated numbers — 4.8, 2.4 and 0.9 mV·µm for 0.18 µm, 45 nm and 22 nm process classes — but deliberately never exercised the formula on an actual device. This bench is that device. Every inverter you have built in this chapter is a pair of MOSFETs with some threshold voltage; Pelgrom's law says two of them, built side by side on the same die, will never have exactly the same one. The random part of that mismatch shrinks with the square root of gate area, exactly as it did for the resistor-versus-transistor comparison in the interlude — only now it is VTH itself doing the varying, and VM that inherits the spread.

A single inverter used as a logic gate does not care. Its output only has to land unambiguously on one side of the next gate's own switching threshold; a few millivolts of VM spread across a billion transistors is invisible to a 1-or-0 decision. That is exactly why logic transistors are built at or near a process's minimum size — the smallest area, and therefore the worst absolute matching the process can produce, and nobody has ever needed to fix it.

It becomes a real problem the moment a CMOS pair is asked to do something analogue with that threshold: a self-biased inverter used as a reference, a sense amplifier deciding which bit line is higher, the CMOS mirror chapter 9 already warned you about. There, VM spread is not cosmetic — it is the whole error budget, and the only lever that shrinks it is the one Interlude II priced: area.

Commit before you touch anything

You keep the same W/L ratio (so drive strength and VM are unchanged) but scale both W and L up together, growing the device's area. What happens to the piece-to-piece spread in VM across many copies of this inverter?

Answer: A. W/L sets the nominal VM; the area WL, independent of that ratio, sets how tightly a whole batch of nominally identical inverters agree with each other. The bench holds ratio fixed and grows W and L together, and σ(VM) falls exactly as 1/√area, the same law, on the same bench, that chose an inverter's own transistors in lesson 1.

Three debts, paid

To chapter 9: a MOS current mirror has no base-current error at all — a MOSFET's gate draws no DC current, so the exact 1/(1+2/β) correction chapter 9 built an entire lesson around simply does not exist here. But what replaces it is worse in a different currency: current mismatch between two MOS mirror legs runs as ΔI/I ≈ 2ΔVTH/VOV, and this bench's own numbers show why that stings — a few millivolts of VTH spread sits directly against an overdrive of only a few hundred millivolts, where a BJT's exponential law effectively divided its own mismatch by VT, a much larger number in the denominator. No base current, and a worse matching problem: both true, for the same underlying reason.

To chapter 9, again — the rail. A saturated MOSFET needs VDS ≥ VOV just to stay in the region this bench has depended on all chapter. At this bench's default sizing that is roughly 0.48 V of headroom per stacked device, on a 1.8 V rail. Stack a cascode — two devices in series doing one job — and you have spent over half the rail on overdrive alone, before a single other stage gets a volt to work with. Bipolar's VCE,sat of a few hundred millivolts was cheap by comparison; that is the "rail too low to stack cascodes freely" chapter 9 promised you.

To chapter 10: the same long-tailed pair, rebuilt from this chapter's devices, has a tail and a load that are both MOS — and chapter 10's CMRR numbers do not carry over, because they leaned on VA/VT ≈ 2,900. The MOS equivalent, gmro, is this bench's own lesson-1 gain figure: about −52 at VM, two orders of magnitude smaller. Every dB of CMRR chapter 10 built from that ceiling shrinks by the same two orders of magnitude the moment the devices are MOS instead of bipolar.

Interlude II priced exactly this trade in dollars. A tighter match costs area; area costs money on a wafer that is priced per square millimetre regardless of what sits in it. One sentence, not a lecture: everything this lesson's bench shows for free, in microvolts, has a line item on the interlude's chart.

In the wild

SRAM bit cells. Built at the smallest area a process allows, for density — and threshold mismatch between the cell's own transistors is a leading cause of read/write failures at the tails of a large memory array, which is why SRAM cells are sized slightly above absolute minimum despite the area cost.

Comparators and sense amplifiers. Reach for exactly the enlarged, Pelgrom-priced devices this lesson describes, right next to logic built at minimum size two transistors away on the same die.

Why analogue and digital blocks look so different on a die photo. Interlude II already showed this from the cost side; this lesson is the physical reason the photo looks that way at all.

Before you move on

Two CMOS process classes are compared: one with AVT = 2.4 mV·µm, one with AVT = 0.9 mV·µm. At the same physical device area, which has the tighter VTH match?

σ(ΔVth) = AVT/√(WL) falls directly with AVT at fixed area. Scaling did genuinely shrink the raw matching coefficient — it just did not make tight matching free, since minimum device area shrank right alongside it.
Bench 06 · Pelgrom on a real MOS bench —
● Locked until you commit a prediction above.
1.00 µm
0.1 µm1 µm100 µm
Gate area WL—
σ(ΔVth) per device—
σ(VM) across many copies—
gmro here (cf. bipolar's ≈2,900)—
✓

Checkpoint

six questions · two of them reach back before this chapter

1. At the switching threshold VM, a well-designed inverter's two transistors are…

That is the one point on the curve where the inverter briefly behaves like a two-transistor amplifier rather than a switch.

2. A CMOS gate sitting steady at either logic level draws, at DC (ignoring leakage)…

The short-circuit spike of lesson 2 is confined to a narrow band of Vin near VM; at either rail one device is hard off.

3. Doubling every transistor's width on a chip, everything else fixed, roughly…

E = CLVDD2 per charging edge, independent of W. Width buys delay, not energy — this chapter's misconception, corrected.

4. Lowering VTH to speed a chip up, at fixed VDD and frequency, moves the dynamic/static crossover frequency…

Subthreshold current is exponential in overdrive; a couple of hundred millivolts of VTH is worth a couple of decades of leakage.

5. ch 9 A MOS current mirror, compared with chapter 9's bipolar one, has…

A real advantage (no gate current) and a real cost (worse relative matching) arrive together — chapter 9's own forward reference, paid off here.

6. ch 10 Why don't chapter 10's bipolar CMRR figures carry over to the same pair built in CMOS?

This chapter's own bench measured gmro around −52 — two orders of magnitude below the bipolar ceiling every earlier CMRR and gain figure in this course was built on.
0 / 6
Answer all six.

Every word this chapter introduced

CMOS inverter L1
An NMOS and a PMOS, gates tied together as the input, drains tied together as the output. The complementary pair every digital logic gate is built from.
Switching threshold VM L1
The input voltage where the transfer curve crosses Vout = Vin. Both devices sit in saturation there, briefly acting as a two-transistor amplifier rather than a switch.
Short-circuit (crowbar) current L2
The current that flows rail-to-rail through both devices at once, confined to a narrow band of Vin near VM. Zero at either logic level, since one device is always off there.
Dynamic power L3
α·CLVDD2·f. The energy to charge and discharge a load capacitance each transition, independent of transistor width; width sets only how fast that energy is delivered.
Propagation delay tp L4
Time for the output to cross VDD/2 during a transition. Falls with transistor width and rises with load capacitance, in contrast to dynamic energy, which depends on neither width.
Static (leakage) power L5
Power drawn by "off" devices' subthreshold conduction, independent of switching frequency. Exponential in VTH, and the reason lower thresholds are not a free speed lever.
Crossover frequency f* L5
The clock frequency where dynamic and static power are equal. Above it, dynamic dominates; below it, an idle chip's leakage floor takes over.
Pelgrom's law, on a MOS bench L6
σ(ΔVth) = AVT/√(WL), first stated in Interlude II, now shown moving a real inverter's VM. Logic transistors sit at minimum area and pay for it in absolute mismatch that nobody needs to care about; analogue MOS pairs pay the same law in area, and Interlude II already priced that area in dollars.

Where this goes next

CH 12

The Loop Bench

The last chapter. The high-impedance node chapters 9 and 10 built is where the compensation capacitor lands, chapter 8's slew rate turns out to be one number this chapter also measures, and the same amplifier will turn out to be stable or unstable depending on what you close the loop with — a property of the loop, not the device.

CH 7

Back to the FET Bench

Worth rereading now. Every device in this chapter's inverter is exactly that chapter's square-law FET; the gain ceiling that fell with overdrive there is the same −52 this chapter just measured at VM.

INTERLUDE II

Back to The Money

Worth rereading now too. Pelgrom's law sat unexercised there; bench 6 just ran it on a real device, and the dollar figures the interlude quoted are the price of the area that bench spends.

CH 9

Back to The Mirror Bench

The base-current-versus-matching trade in lesson 6 was promised there. It is worth seeing the bipolar mirror's 1/(1+2/β) correction again, now that its MOS replacement has no equivalent term at all.

About the simulations. Every bench here uses the same square-law MOSFET model as chapter 7 — fetID(VOV, VDS, dev), continuous by construction across the saturation/triode boundary — applied twice, once per device. The PMOS is not a separate model: it is fed the same function with source-referenced magnitudes, VSG in place of VGS and VSD in place of VDS, exactly as chapter 9 discovered that bjt() must be given junction-voltage differences rather than raw terminal voltages to get a PNP right. This is that same sign-convention trap, in its third disguise; the standing check here is that a PMOS with VSG = 1.38 V, VSD = 0.9 V carries exactly the current an NMOS with the matching VGS, VDS does. The inverter's DC operating point is not found by damped iteration but by bisection on Vout, on the residual IN(Vout) − IP(Vout) — provably monotonic, since IN is non-decreasing and IP non-increasing in Vout — which is why the two current traces on bench 2 sit exactly on top of one another rather than merely close. The transient benches (3 and 4) integrate dVout/dt = ±I/CL with fixed-step RK4, sized per call from a constant-current delay estimate so the same resolution is used whether the load is 2 fF or 200 fF; halving the step again moves every reported number by under 0.01%. The energy figure in bench 3 was checked two ways — direct numeric integration of I·VDD over the charging edge, and the closed-form CLVDD2 — and the two agree to five significant figures at every width setting tried, which is the numeric proof behind this chapter's misconception. Bench 6's σ(VM) is not a separate formula: it is a numerical derivative of the same bisection solver used everywhere else in the chapter, dVM/dVTH found by a central difference and combined in quadrature with Interlude II's own AVT constants, so no new sensitivity formula was hand-derived and possibly gotten wrong. Three honest simplifications. First, the subthreshold leakage in bench 5 is a single illustrative exponential in one device's threshold; it does not separately model NMOS and PMOS leakage, DIBL, or leakage's own dependence on VDS and temperature, all of which move a real chip's static floor. Second, channel-length modulation λ is held fixed across the width and process-node controls; in a real process it rises as channel length shrinks, which would make bench 6's gmro fall further at smaller nodes than shown here. Third, bench 3 and 4's load is a fixed external capacitor; a real gate driving another gate also charges the driving transistors' own parasitic capacitance, which grows with width and is the reason "just make it bigger" has a real ceiling that this model does not show.