The Difference Bench  / Chapter 10
0 / 6 done
Mini-EE · Chapter 10 of 12 · six 13–15 minute lessons

Common-mode rejection is not a property of the pair. It belongs to the tail.

Two transistors, emitters tied together, fed from below by a single current. It is the input stage of every op-amp you have ever used, the front end of every instrumentation amplifier, and the comparator in every ADC. Everyone learns that it amplifies the difference between its inputs and ignores what they have in common. The second half of that sentence is false in an interesting way — and the number that says how false comes entirely from the last chapter, not this one.

Assumes
Chapters 1 to 9
Per lesson
13–15 min
The number
CMRR = gmRtail
Next
Interlude II · The Money
01

The tail decides who gets what

13 minutes · a constraint, not a supply, and the 100 mV that switches it
Recall From chapter 9: what single number describes the quality of a current source, and what is it for a plain grounded-emitter one at 1 mA? show answer

Take two identical NPN transistors. Tie their emitters together at one node. Put a collector resistor on each, up to the positive rail. Now, instead of a resistor from that shared emitter node down to the negative rail, put a current source there — the one you built in chapter 9. That is the whole circuit. It is called a differential pair, or a long-tailed pair, and the current source is the tail.

Everything follows from one observation. The tail insists on a fixed total current. Whatever Q1 takes, Q2 cannot have. The tail is not a supply that the transistors draw from as needed; it is a constraint that they have to divide between them. So the only question the circuit can answer is: in what proportion?

That proportion is set by the exponential you have been using since chapter 1. Each emitter current is IS exp(VBE/VT), and both devices share the same emitter node, so the ratio of the two currents is exp((v1−v2)/VT). The shared node drops out entirely. Only the difference between the two base voltages survives.

Commit before you touch anything

The tail holds 1 mA. Both bases start at 0 V, so each transistor carries half. You raise one base by 100 mV and lower the other by the same, a difference of 200 mV. What happens?

Answer: B. The bench reads 0.9940 mA and 0.0005 mA — 99.95% of the tail on one side. The whole useful input range of a bipolar pair is about ±100 mV, and it is linear over rather less than that. Note what did not happen: the sum stayed at 0.994 mA the whole way. Answer C is the instinct worth killing early. Raising a base does not fetch more current; it takes current from the other transistor.

Four VT is the whole story

Write the fraction of the tail flowing in Q1 and it comes out as 1 / (1 + e−vid/VT), where vid is the difference between the bases. That is a logistic curve — the same S-shape as tanh, which is how Sedra writes it. It has no adjustable width. The only scale in it is VT, which is 25.9 mV and which you do not get to choose.

So the pair is 50:50 at zero, about 73:27 at one VT, and 98.2:1.8 at four VT, which is 103.5 mV. Beyond that there is nothing left to steer. Set the bench's collector resistors to zero and the measured split matches that formula to four decimal places at every point. Leave them at 8 kΩ and it drifts by up to about nine parts in a thousand, because the collectors are moving as the current shifts and the Early effect from chapter 5 makes each transistor slightly current-dependent on its own collector voltage. That gap is real physics, not solver error, and it is the first hint that the two collectors are not passive spectators.

A differential pair is a switch that has been persuaded to be an amplifier. Its natural behaviour is to dump the entire tail down one side. The narrow band near the middle where it responds in proportion is the part we exploit, and chapter 5's warning applies with force: “small signal” here means a few millivolts, not a few volts.

In the wild

Every ECL and current-mode logic gate ever made. They are differential pairs run deliberately as switches, never as amplifiers. Because the transistors never saturate and the tail current never changes, ECL was the fastest logic family for thirty years — and burned power continuously for it.

The comparator in a flash ADC. A differential pair with 100 mV between its inputs is already fully decided. That is why a comparator gives you a clean digital answer from an analogue difference of a few tens of millivolts.

Why a guitar fuzz pedal built round a pair clips so symmetrically. The tanh curve saturates identically in both directions, unlike the single-transistor stage of chapter 5 whose top and bottom clip differently.

Before you move on

You raise both bases of a differential pair by 200 mV. What happens to the total current through the two transistors?

The emitter node rises by very nearly the same 200 mV, both VBEs end up where they started, and the tail current source holds. It does not hold perfectly, and the amount by which it fails is the entire subject of lessons 3 and 4.
Bench 01 · dividing a fixed tail BALANCED
● Locked until you commit a prediction above.
0 mV
−200 mV0+200 mV
1.00 mA
0.2 mA1 mA2 mA
IC1—
IC2—
Sum—
Share in Q1—
02

Two inputs arriving on the same two wires

15 minutes · the misconception this chapter is built on
Recall From chapter 5: what is gm at a collector current of 0.5 mA, and what is the gain of a stage with an 8 kΩ collector resistor? show answer

Two voltages arrive at the two bases. Rather than treat them as v1 and v2, split them into the two things the circuit actually distinguishes: their difference vid = v1 − v2, and their average vicm = (v1 + v2)/2, called the common-mode input. Any pair of inputs can be written this way, and the two components pass through the circuit by completely different routes.

The differential route you already know. A difference vid tilts the split, one collector current rises by gmvid/2 and the other falls by the same, and each collector moves by that times RC. At 1 mA of tail each device carries 0.4969 mA, so gm is 19.21 mS and the bench measures a single-ended gain of −73.23 and a collector-to-collector gain of −146.47. Those two numbers are in the ratio 2.000000, exactly, because the two halves move by equal and opposite amounts.

The misconception

“A differential pair rejects the common mode, and how well it does so is a measure of how good the pair is.” Both halves of that need work. The rejection is not perfect — it is a finite number you can measure, and the bench measures it at −0.0471 for a common-mode input against −73.23 for a differential one. And the part that will take three more lessons: the number has nothing to do with the pair. It is not set by how well Q1 and Q2 match, nor by their current, nor by RC. Lesson 3 finds where it actually comes from, and it is not in this drawing.

Play the two modes against each other on the bench and the asymmetry is hard to miss. Sweeping the difference across 80 mV throws the collectors apart by volts. Sweeping the common mode across 14 V — a range 175 times wider — moves them by less than a volt, together, in the same direction.

Commit before you touch anything

The bench's differential gain is −73.2 at one collector. You now drive both inputs together with a 1 V common-mode signal. How far does one collector move?

Answer: B. The common-mode gain is −0.0471, so 1 V in gives 47.1 mV out at each collector, in step. Two things to notice. It is less than unity, so the circuit does attenuate the common mode — but it is not zero, and 47 mV of unwanted output is enormous next to the microvolts of real signal a sensor bridge might deliver. And because both collectors move together, the difference between them barely changes at all: that is why taking the output differentially is a different proposition from taking it at one collector, which lesson 5 makes precise.

Why anyone cares

The reason this decomposition earns its own vocabulary is that in practice the thing you want is small and differential and the thing you do not want is large and common. A strain gauge bridge puts out a few millivolts of difference sitting on 2.5 V of common mode. An ECG electrode pair carries about a millivolt of heart signal on top of a volt or more of mains hum picked up by the patient, identically, on both leads. A microphone on a long balanced cable picks up interference equally on both conductors precisely so that a differential input can throw it away.

In every one of those cases the useful ratio is not the gain. It is the gain divided by the common-mode gain, and that ratio has a name we will earn properly in lesson 4.

DriveRange sweptOutput moveGain
Differential80 mV5.86 V−73.23
Differential, collector to collector80 mV11.72 V−146.47
Common mode14 V0.66 V−0.0471
The same two wires carry both. Nothing at the input distinguishes them; the decomposition is something you do on paper. The circuit performs the separation by giving the two components wildly different paths to the output, and the whole art is in widening that difference.

In the wild

The XLR cable on a stage microphone. Three pins: ground, and two signal conductors carrying the audio as a difference. Fifty metres of cable next to a lighting dimmer picks up hum on both conductors equally, and the mixing desk's differential input subtracts it.

Ethernet, USB, HDMI, CAN bus. Every fast digital interface built since about 1990 is differential, for the same reason and with the same arithmetic.

The two input pins of the op-amp in chapter 8. They are the bases of Q1 and Q2. The “+” and “−” markings are not a convention chosen for convenience; they are which transistor you are wired to.

Before you move on

Inputs of 2.010 V and 2.004 V arrive at a pair. What are the differential and common-mode components?

The difference is 6 mV and the average is 2.007 V. This is the ordinary case: a tiny wanted signal riding on a large unwanted one, in a ratio of about 335 to 1. Whether the circuit can recover the 6 mV depends entirely on the ratio in lesson 4.
Bench 02 · the two modes, on the same axes DIFFERENTIAL
● Locked until you commit a prediction above.
8.00 kΩ
2 k9 k16 k
Ad, one collector—
Ad, collector to collector—
Acm, one collector—
Ratio—
03

The common mode escapes through the tail

14 minutes · chapter 9's output resistance, wearing a different hat
Recall From chapter 9: a transistor current source carrying 1 mA with VA = 75 V — what is its output resistance, and what happens if you stack a cascode on it? show answer

Follow a common-mode signal through the circuit and there is exactly one place it can get out. Raise both bases by Δv. The emitter node, which sits one VBE below them, rises by very nearly the same Δv. If the tail were a perfect current source, nothing else would happen and the collectors would not move at all.

But the tail is a real circuit with a finite output resistance Rtail, so raising the voltage across it by Δv raises its current by Δv/Rtail. That extra current splits equally between the two transistors, and each collector falls by half of it times RC. So:

  1. Both bases move by Δv; the emitter node follows.
  2. The tail current changes by Δv / Rtail — the only thing in the circuit that noticed.
  3. Half of that appears in each collector, so each output moves by −Δv RC / 2Rtail.
  4. Therefore Acm = −RC / 2Rtail, and it is zero only if Rtail is infinite.

Every symbol in that result comes from chapter 9. Rtail is precisely the output resistance you spent that chapter learning to specify, raise and pay for. The differential pair does not introduce a new problem; it inherits the old one and gives it consequences.

Commit before you touch anything

The bench holds the tail current at exactly 1.000 mA and lets you swap the tail between a resistor, a chapter-9 mirror, and a cascoded mirror. What happens to the differential gain as you switch?

Answer: B. The bench reads −73.23 for all three tails — identical to five figures, along with the same emitter node at −0.635 V and the same collectors at 6.02 V. What moves is Acm: −0.4227 for the 9.365 kΩ resistor, −0.0471 for the mirror at 83.7 kΩ, and −2.1×10−6 for the cascode at 13.1 MΩ. A factor of 200,000 in rejection for no change whatever in gain. That is the shape of the whole chapter.

Where the input range comes from too

Drag the common-mode marker to the ends of its travel and the traces collapse — but not at the same place for all three tails, and not for the same reason. With the mirror, the floor arrives near −9.15 V: the emitter node has pushed the tail transistor down to about 0.2 V of VCE and its output resistance is gone. That is chapter 9's compliance floor, arriving here as an input specification. The cascode, which needs a second VCE stacked underneath, gives up around −8.35 V — roughly 0.8 V of input range surrendered in exchange for its extra 87 dB. The resistor tail has no compliance floor to hit at all; it simply delivers less and less current as the emitters approach the negative rail until there is nothing left to amplify with.

At the top the three agree, because the limit is no longer the tail's: near +5.9 V the collectors have come down to meet the rising bases and Q1 and Q2 saturate themselves. So the range is bounded below by whatever you chose for the tail and above by the pair — two unrelated mechanisms, which is why the range is asymmetric and why datasheets quote it as a range rather than a ± number. It is also the first place in this chapter where the better tail visibly costs you something.

The better tail buys nothing you can see on an oscilloscope with one probe. Its entire contribution is to a quantity you only observe by driving both inputs together — something no single-ended measurement will ever show you. This is why common-mode rejection is so often specified and so rarely checked.

In the wild

Why a cheap op-amp and an expensive one can have the same gain-bandwidth and very different price. Open the die photographs and the difference is often in the tail: a resistor or a plain mirror in one, a cascoded or degenerated source in the other.

The instrumentation amplifier in a weighing scale. A load cell delivers about 2 mV per volt of excitation, sitting on half the excitation voltage as common mode. Every part of that front end exists to make Rtail large.

Why an ECG front end is specified at 100 dB and up. A millivolt of heart signal underneath a volt or two of 50 Hz hum needs rejection in the hundred-thousands, which a resistor tail cannot begin to supply.

Before you move on

You double Rtail and leave everything else alone. What happens?

Acm = −RC/2Rtail, so it halves. The differential signal never sees Rtail at all: the two halves move in opposite directions, the emitter node stays put, and as far as a difference is concerned that node might as well be grounded.
Bench 03 · three tails, one differential gain ACTIVE
● Locked until you commit a prediction above.
0.00 V
−9.8 V−1.6 V+6.6 V
Rtail—
Ad, one collector—
Acm—
Rejection ratio—
04

CMRR, and the number you cannot buy with current

15 minutes · gmRtail, and why it will not move
Recall From chapter 5: what is the largest voltage gain a single bipolar stage can have, and what sets it? show answer

Put the two gains together. The common-mode rejection ratio is the differential gain divided by the common-mode gain, both taken at the same output:

CMRR = Ad / Acm = (gmRC/2) / (RC/2Rtail) = gmRtail

RC cancels. That is not an approximation and it is not a coincidence — the collector resistor is in both numerator and denominator because both signals leave through the same collector. Whatever you do to the load, you do to both, and the ratio is untouched.

Now push it further, because gm and Rtail are not independent either. Each pair transistor carries half the tail, so gm = Itail / 2VT. And if the tail is a transistor, Rtail = VA / Itail. Multiply:

CMRR = (Itail/2VT) × (VA/Itail) = VA / 2VT ≈ 1,450

The current cancels too. Turning the tail up raises gm and lowers Rtail by exactly the same factor. You have met this shape before: chapter 9's active load had a gain that would not move with current for the same reason. Half of chapter 5's VA/VT ceiling, arriving as a rejection ratio.

Commit before you touch anything

You raise the tail current from 0.15 mA to 2.5 mA — a factor of 16.7 — with the mirror tail and RC fixed. The differential gain goes from −11.5 to −169.3. What does CMRR do?

Answer: C. Gain up 14.7×, rejection down 11%. And the residual 11% is not a failure of the rule: look at the gmRtail meter, which runs 1610.6 to 1606.6 across the whole sweep — flat to a quarter of a percent. The small drift in the measured CMRR tracks the collector voltage, which falls from 9.40 V to 0.08 V as the current rises, taking the transistors' own ro down with it. Switch RC instead of the current and you get the identical drift over the identical collector-voltage range, which is how you can tell it is ro and not the tail.

Decibels, and what real parts achieve

CMRR is almost always quoted in decibels, as 20 log10 of the ratio. The bench's mirror-tailed pair reads 1,553, which is 63.8 dB. The resistor-tailed version reads 173, or 44.8 dB. A µA741 specifies 90 dB, an OP07 120 dB, and a good instrumentation amplifier 130 dB at DC. Those upper numbers are far beyond anything a single pair with a plain tail can reach, which tells you the extra decibels are bought elsewhere — partly with the cascoded tail of lesson 3, partly with trimming, and partly by taking the output differentially, which lesson 5 shows is a different measurement altogether.

One honest note about the bench's cascode reading. It shows 150.8 dB, which no real part achieves. The model has perfectly matched devices and no leakage, so once Rtail reaches 13 MΩ there is nothing left to limit the number. In silicon, mismatch takes over long before that. Treat the cascode figure as showing you which way the arrow points, not as a specification.

ItailAdgmRtailCMRR
0.15 mA−11.491610.664.18 dB
0.50 mA−37.571609.364.04 dB
1.00 mA−73.231608.363.83 dB
2.50 mA−169.271606.663.17 dB
You cannot buy rejection with current. Nor with bigger collector resistors, nor by matching the pair more carefully. The only lever that moves CMRR at a single-ended output is Rtail, and raising Rtail is entirely a chapter 9 problem. That is the sense in which this chapter is a consequence of the last one rather than a new subject.

In the wild

Why datasheets quote CMRR at DC and again at 1 kHz, and why the second number is worse. Rtail is shunted by the tail transistor's collector capacitance, so it falls with frequency and takes the rejection with it. Mains hum at 50 Hz is rejected better than a switching supply's ripple at 100 kHz.

Why a battery-powered instrument sometimes measures better than a mains one. Not the noise floor — the common mode. Floating the whole front end removes the signal the CMRR was going to have to fight.

The VA/2VT number turns up in the MOS world too, but with a much smaller VA and a different overdrive, which is one of several reasons chapter 11's circuits do not simply inherit these figures.

Before you move on

Your pair has 60 dB of CMRR. You need 80 dB. Which change gets you there?

80 dB is 10,000, so you need ten times the rejection, which means ten times Rtail. A cascode gives you about β of it — far more than you asked for — at the price of roughly a volt of common-mode range. A and B cancel out of CMRR entirely; D is answered in lesson 5, and it is not what a single-ended output measures.
Bench 04 · gain moves, rejection does not FLAT
● Locked until you commit a prediction above.
1.00 mA
0.15 mA0.6 mA2.5 mA
Ad—
Acm—
CMRR—
gmRtail—
05

Mismatch, offset, and two different rejections

14 minutes · what matching actually buys, and what it does not
Recall From chapters 1 and 9: how much does collector current change for a 1 mV error in VBE? show answer

Everything so far assumed the two halves were identical. They are not. Make the two collector resistors differ by 1%, or the two transistors differ by 1% in emitter area, and the pair no longer balances at zero input. You have to apply a small deliberate difference to bring the outputs back together, and that voltage is the input offset voltage, VOS.

It is smaller than you would guess, and for a good reason. The exponential that made the pair so sensitive in lesson 1 works in your favour here: a 1% current error needs only VT ln(1.01) = 257 µV of VBE to correct. The bench measures 257.4 µV for a 1% resistor mismatch and 257.4 µV for a 1% device mismatch — the same number, because both are asking the same exponential the same question.

Commit before you touch anything

You mismatch the two collector resistors by 5%. What happens to the CMRR measured at one collector?

Answer: C. Single-ended CMRR is gmRtail and neither term knows anything about matching. What the 5% mismatch does produce is 1.26 mV of input offset, and a collapse in the other rejection figure — the one measured collector to collector, which falls from unlimited to 97.4 dB. There are two CMRRs here and they measure different diseases.

The two rejections

Take the output at one collector and a common-mode input reaches it through the tail, exactly as lesson 3 described. Matching is irrelevant: both halves are equally affected either way. CMRR is gmRtail, full stop.

Take the output between the collectors and the picture inverts. A common-mode input pushes both collectors the same way, so their difference does not move at all — unless the two sides respond by different amounts, which happens only if they are mismatched. With a perfectly matched pair the model gives exactly zero and the ratio is unbounded. Introduce mismatch and it becomes finite, in inverse proportion: 123.2 dB at a quarter of a percent, 111.2 dB at one percent, 97.4 dB at five. Every halving of the mismatch buys 6 dB.

This is why the two specifications on a datasheet behave so differently, and why an instrumentation amplifier is sold on its matching while a general-purpose op-amp is sold on its tail. It is also, bluntly, why matching is worth money.

RC mismatchVOSCMRR, one collectorCMRR, differential
001,553unbounded
0.25%64.6 µV1,554123.2 dB
1%257.4 µV1,554111.2 dB
5%1.262 mV1,55797.4 dB
Why offset drifts
VOS = VT ln(1+δ) is proportional to VT, which is proportional to absolute temperature. An offset of 1 mV at 300 K drifts by about 3.3 µV per degree, and no amount of trimming at one temperature removes that slope. It is why precision op-amps are specified for drift separately from offset.
Matching is a manufacturing purchase, not a design choice. You cannot specify it in a schematic. It comes from laying the two devices out interdigitated, in the same orientation, at the same temperature, on the same die, in the same process step — and from paying for the area and the process control that makes that hold. Interlude II, which comes next, is about exactly what that costs and why it did not get cheaper when digital did.

In the wild

The offset null pins on a 741. Pins 1 and 5 let you trim a potentiometer across the input stage's load, deliberately mismatching it to cancel the mismatch already there. You are nulling one imbalance with another.

Chopper and auto-zero amplifiers. Rather than match better, they measure their own offset thousands of times a second and subtract it, reaching microvolt offsets from ordinary transistors. The cost is switching noise, which is the trade every chopper makes.

The common-centroid layout in any analogue chip photograph. Two devices laid out as four half-devices in a cross pattern, so that a linear gradient in temperature or oxide thickness across the die cancels. That pattern exists solely to fight the mismatch in this lesson.

Before you move on

A pair has 2% device mismatch, giving about 510 µV of offset. You double the tail current. What happens to the offset?

VOS = VT ln(1+δ) contains no current at all. Offset is a property of the mismatch and the temperature, and the only ways to move it are to match better, run colder, or cancel it actively.
Bench 05 · a pair that does not balance at zero MATCHED
● Locked until you commit a prediction above.
0.00 %
−5%0+5%
Offset VOS—
VT ln(1+δ)—
CMRR, one collector—
CMRR, differential—
06

The mirror load, and where chapter 8's op-amp came from

15 minutes · one component doing two jobs, and a gain of 1,540
Recall From chapter 8: the virtual short between an op-amp's inputs — is it a property of the device, and what actually produces it? show answer

Two problems are left. The collector resistors are a poor load, for exactly the reason chapter 9 gave: to get a large small-signal resistance you must drop a large DC voltage you do not have. And taking the output at one collector throws away half the signal, since the other collector carries an equal and opposite copy.

One component solves both. Replace the two resistors with a PNP current mirror: its diode-connected side sits on Q1's collector, its output side on Q2's. Now Q1's signal current is copied across and added to Q2's at the output node, so the full differential current appears at a single terminal. The mirror is simultaneously the load and the differential-to-single-ended converter. This is the arrangement Sedra calls an active-loaded differential pair, and it is the input stage of essentially every bipolar op-amp built.

The gain is chapter 9's number: gm times whatever resistance appears at the output node, which is now the NPN's ro in parallel with the PNP's. The bench measures 1,539.6 against a hand calculation of gm(ron∥rop) = 1,540.3, with ron at 155.5 kΩ and rop at 154.3 kΩ. Compare it with 73.2 from an 8 kΩ resistor at one collector: twenty-one times better, of which a factor of two is the mirror recovering the wasted half and the rest is chapter 9's load.

Commit before you touch anything

With the mirror load, how much differential input does it take to drive the output from one rail to the other?

Answer: B. Six millivolts takes the output from 0.39 V to 9.61 V. That curve should look extremely familiar: it is chapter 8's opening bench, the one where the op-amp sat against a rail until the inputs agreed to within a fraction of a millivolt. You are now looking at what was inside that black box. And the sentence chapter 8 built its own misconception around — that the virtual short is a consequence of enormous gain rather than a property of the device — is visible here as a slope you can measure.

A systematic offset, and where it comes from

Look at where the curve crosses mid-rail: not at zero, but at −3.18 mV. That is a systematic offset — present with perfectly matched devices, built into the topology, and much larger than the random offsets of lesson 5. It is tempting to blame the mirror's base current, which chapter 9 showed makes the output run 1/(1+2/β) low. Raise the PNP's β on the bench from 150 to 4,000 and the offset only improves from −3.18 mV to −2.85 mV, so base current accounts for about a tenth of it.

The rest is the Early effect. Q1's collector is pinned one VEB below the positive rail at 9.36 V, while Q2's sits wherever the output is, near 5 V. Two transistors with the same VBE and four volts of difference in VCE do not carry the same current, and the input must be tilted to make up the difference. That is why a real op-amp does not use the plain mirror drawn here: it degenerates it, or adds a base-current-cancelling transistor, or both.

One more thing to try. Sweep the tail current and watch the gain: 1,540 at 0.3 mA, 1,540 at 1 mA, 1,539 at 2 mA. Flat, for chapter 9's reason — gm rises with current and both ro fall by the same factor. And it lands at 1,540 against chapter 5's absolute ceiling of 2,899, short by the same kind of margin as chapter 9's 1,251, because a load transistor's ro is never much better than the amplifying transistor's own.

This is the join between the two halves of the course. Chapter 8 measured an op-amp's open-loop gain, saturation and virtual short from outside. This bench produces all three from four transistors and a tail. Nothing new was needed: gm from chapter 5, ro and the mirror from chapter 9, the pair from lesson 1.

In the wild

The µA741 die. Its input stage is this circuit with two extra transistors: a cascode pair for breakdown protection, and a base-current-cancelling device in the mirror to attack exactly the systematic offset above.

Why an op-amp's open-loop gain is specified as a minimum, never a typical. It is gm(ron∥rop) multiplied by the second stage, and every term in it is a process parameter that varies wafer to wafer.

The comparator you use as an op-amp, and regret. A comparator is this circuit deliberately optimised for switching rather than linearity — no compensation capacitor, often no linear region worth the name. The topology is nearly identical and the applications are not interchangeable.

Before you move on

Why does a mirror load give twice the gain of a current-source load on one collector alone?

The two collector currents are equal and opposite, so a load on one collector uses half the available signal. The mirror turns Q1's half around and delivers it to the same node — converting differential to single-ended and recovering the factor of two in one component.
Bench 06 · chapter 8's open-loop curve, from the inside LINEAR
● Locked until you commit a prediction above.
1.00 mA
0.3 mA0.8 mA2 mA
150
504504000
Gain at balance—
ron ∥ rop—
Systematic VOS—
gm—
✓

Checkpoint

six questions · two of them reach back before this chapter

1. A differential pair with a 1 mA tail has 200 mV between its bases. The two collector currents are about…

The pair is fully switched by about ±100 mV, and the sum never exceeds what the tail supplies. C fails on both counts.

2. The common-mode gain at one collector is…

A is true only of the collector-to-collector output. C is the differential gain. The common mode leaves through the tail's finite output resistance and nowhere else.

3. Holding the tail current fixed at 1 mA and swapping a 9.4 kΩ resistor tail for a mirror tail, the differential gain…

The bench reads −73.23 for both. A difference signal never sees the tail, because the emitter node does not move for it.

4. ch 9 A cascode raises a current source's output resistance by roughly…

Which is why the cascoded tail on bench 3 reads 13.1 MΩ against the plain mirror's 83.7 kΩ. The price, then as now, is about a volt of range.

5. ch 5 The intrinsic gain ceiling VA/VT is about 2,900. The CMRR of a pair with a plain transistor tail comes out at VA/2VT because…

gm = Itail/2VT and Rtail = VA/Itail, so the product is VA/2VT ≈ 1,450 with the current cancelling out entirely. RC is in both gains and cancels too.

6. You mismatch the collector resistors by 1%. Which figure moves?

257 µV of offset appears, and the differential-output rejection falls from unbounded to 111 dB. Single-ended CMRR is gmRtail and moves from 1,553 to 1,554 — which is to say, not at all.
0 / 6
Answer all six.

Every word this chapter introduced

Differential pair L1
Two matched transistors with their emitters joined and fed by a single current source. Responds only to the difference between its base voltages, because the shared emitter node cancels out of the ratio of the two exponentials.
Tail L1
The current source under the joined emitters. A constraint on the total, not a supply the transistors draw from: whatever one takes, the other cannot have.
Full steering L1
The condition where essentially the whole tail flows in one device. Reached at about four VT, or 103 mV, at which point 98.2% is on one side.
Differential input vid L2
The difference between the two base voltages, v1 − v2. The component the circuit is built to amplify.
Common-mode input vicm L2
The average of the two base voltages. The component the circuit is built to ignore, and only partly succeeds in ignoring.
Common-mode gain Acm L3
−RC/2Rtail at a single collector. The common mode reaches the output by changing the tail current, and by no other route.
Common-mode input range L3
The span of vicm over which the pair still works. Bounded below by the tail's compliance floor and above by the pair's own saturation — two unrelated limits, hence an asymmetric range.
CMRR L4
Ad/Acm = gmRtail, usually quoted in decibels. Independent of RC, of tail current, and of how well the pair is matched. With a plain transistor tail it reduces to VA/2VT.
Input offset voltage VOS L5
The differential input needed to balance a mismatched pair. VT ln(1+δ) for a fractional mismatch δ, whether the mismatch is in the loads or the devices. Independent of current; proportional to absolute temperature.
Systematic offset L6
Offset built into a topology rather than caused by random mismatch. In the mirror-loaded pair it is −3.18 mV, about a tenth from mirror base current and the rest from the two collectors sitting at different voltages.
Active-loaded pair L6
A differential pair whose collector resistors are replaced by a current mirror, which serves as both a high-impedance load and a differential-to-single-ended converter. Gain gm(ron∥rop). The input stage of most bipolar op-amps.

Where this goes next

INTERLUDE II

The Money

You have just spent a chapter discovering that matching is what you pay for and cannot design. Next: why matched transistors are cheap and matched resistors are not, why analogue did not scale the way digital did, and who captures the value in a chip.

CH 11

The CMOS Bench

The same pair built from MOSFETs, where there is no base current and no β, the matching problem is worse rather than better, and VA is small enough that these CMRR figures do not carry over.

CH 12

The Loop Bench

The high-impedance output node of bench 6 is where the dominant pole goes. Chapter 8's slew rate turns out to be this chapter's tail current dividing into that compensation capacitor.

CH 8

Back to the Op-Amp Bench

Worth rereading now. Open-loop gain, the virtual short, offset and common-mode range were all measured there from outside; bench 6 is the circuit that produced them.

About the simulations. Every bench here solves the Ebers–Moll transport equations from the kit — the same device model as chapters 2 to 9 — with a chapter-specific multi-transistor solver, since a differential pair with a mirror tail and a mirror load is six devices sharing five nodes. As in chapter 9, every unknown is found by bisection on a residual that is provably monotonic in it: the emitter node, each collector node, the mirror's shared base node, the cascode's intermediate node and the output node. The direction each residual moves was written down before the comparison was coded, which is not a formality — the first version of bench 6 had the output-node test inverted, and returned a confident, plausible-looking gain of 0.46. The PNP mirror is handled by passing junction voltages, which are differences, into the same device function, and verified by the standing check that a PNP at VEB = 0.7 V, VEC = 2 V carries exactly the current an NPN does at VBE = 0.7 V, VCE = 2 V. Every quoted number was checked against hand calculation outside the browser before any of it was wired to a control: the current split matches 1/(1+e−vid/VT) to four decimal places with the collector resistors removed, the collector-to-collector gain is exactly twice the single-ended one, the offset matches VT ln(1+δ) to four figures, and bench 6's gain agrees with gm(ron∥rop) to 1,539.6 against 1,540.3. Four honest simplifications. First, ro in this model comes out as (VA+VCE−VBE)/IC rather than the textbook VA/IC, which is why bench 3's mirror tail reads 83.7 kΩ where the shorthand says 75 kΩ, and why measured CMRR is about 1,553 where VA/2VT predicts 1,450. Second, the devices are matched to exactly what the mismatch control says and to nothing else: there is no random scatter, no thermal gradient across the pair and no layout, so the cascoded tail's 150.8 dB is a statement about the model rather than about silicon, where mismatch would take over far below it. Third, the tail mirror's shared base node is solved with the output transistor's base current evaluated at the operating point rather than iterated to convergence with the emitter node; the resulting error is in the nanovolts and does not reach any displayed digit. Fourth, everything is DC. There is no junction capacitance, so nothing here tells you what happens to CMRR at 100 kHz — and it does fall, for reasons chapter 12 takes up.