The FET Bench

A gate that never needs replacing an electron

14 minutes · voltage in, and a parabola instead of an exponential

Recall From chapter 2: why does a bipolar transistor draw base current at all? show answer

Chapter 2 earned that base current the hard way: some carriers crossing the base don’t make it to the collector, and every one that recombines has to be replaced through the base wire. No replacement, no current. It is a real, physical, continuous flow — small, but never zero while the transistor is on.

A field-effect transistor has no such wire to earn. Its control terminal — the gate — is a metal plate sitting over the channel, separated from it by an insulator a few atoms thick. Nothing crosses that insulator at DC. Not a trickle, not a fiction-that-turns-out-to-be-real-but-small like β was. Zero, to the limits of anything you can build on a bench.

Commit before you touch anything

You hold the gate voltage of a MOSFET steady at 4 V above the source and measure the current flowing into the gate lead. What do you read?

Answer: B. The gate readout on the bench never leaves zero, at any gate voltage, at any drain current. That is not an approximation this course is making for convenience — it is the actual device. The only current that will ever flow into a MOSFET gate at DC is the leakage of the insulator itself, and a healthy one is unmeasurable with anything short of laboratory equipment.

So what does the drain current answer to?

Only one thing: the voltage sitting between gate and source, V_GS. Below a threshold V_TH the channel does not exist and the device is off. Above it, the channel current follows a square law:

I_D = k (V_GS − V_TH)² for V_GS > V_TH

Compare that with chapter 1’s diode law and chapter 2’s I_C = I_Se^V_BE/V_T. Both of those are exponentials — brutally steep, doubling for every 18 mV or so. This is a parabola. It is steep too, but in an entirely different way, and the difference is not cosmetic: it changes how far you can push the input voltage before the output stops looking like a scaled copy of it.

Signal on the gate, above the bias point	Second-harmonic distortion	Verdict
40 mV peak	about 0.6%	a straight line for any purpose
100 mV peak	about 1.6%	fine for most things
400 mV peak	about 6.3%	audible, and visible on a scope
1.0 V peak	about 15.6%	badly overdriven

The window is the same shape as chapter 5’s, and about sixty times wider. Expand the square law about the bias point and the second-harmonic term works out to v̂_gs/4V_OV, where V_OV = V_GS − V_TH is the overdrive voltage — exactly chapter 5’s v̂_be/4V_T formula, with V_OV standing in for V_T. The bench below sits at V_OV ≈ 1.60 V. V_T was 26 mV. That is why a FET input stage can swallow a signal that would mangle a bipolar one, and it is a real engineering reason to reach for a FET, not a marketing one. The bench's measured figure will sit a little under this formula at every amplitude, not just large ones — that gap is real too, and lesson 5 names what causes it.

Notice what V_OV is not: it is not a property of temperature the way V_T was. It is a design choice — how far above threshold you decided to bias the gate. Push V_OV up and the linear window gets wider. You will meet the price for that in lesson 5.

In the wild

Why JFETs show up in the front end of audio mixers. A wide, gentle linear window means a FET input stage can accept a hot signal — a drum mic a few centimetres from the skin — without the harmonic buildup a bipolar stage would add first.

Electrostatic discharge and the gate you must never touch bare. That insulator is a few atoms thick precisely because zero gate current is the goal. It is also why a stray static charge from a synthetic carpet can silently punch a hole through it before a device is even wired into a circuit.

Why a MOSFET can sit at the input of a multimeter for years. Zero gate current means zero loading on whatever it’s measuring. A FET-input op-amp buffer, which you will meet properly in chapter 8, borrows exactly this property.

Before you move on

What sets the drain current of a MOSFET operating above threshold?

A is wrong because gate current is zero at DC — there is nothing there to be in proportion to. C is wrong because the physics is genuinely different: a channel of carriers modulated by an electric field follows a square law, not an exponential. The only input that matters is V_GS, and the law relating it to I_D is the parabola above.

Bench 01 · the parabola, and the line through it LINEAR

● Locked until you commit a prediction above.

Signal on the gate 40 mV pk

20 mV400 mV1.0 V

Measured gain—

Gate current—

Distortion—

Theory: v̂/4V_OV—

The transconductance that runs out of breath

14 minutes · g_m grows — just not as fast as you’d like

Recall From chapter 5: what is g_m for a bipolar transistor, and what does it not depend on? show answer

Chapter 5’s g_m came from differentiating an exponential, and the result was almost embarrassingly clean: g_m = I_C/V_T, a straight line through the origin. Double the bias current, double g_m. No device parameter appears anywhere in it.

Differentiate the FET’s parabola the same way and a different shape falls out:

g_m = ∂I_D/∂V_GS = 2k(V_GS−V_TH) = 2k V_OV = 2√(k I_D)

Commit before you touch anything

A FET is biased at 1 mA. You then re-bias it at 4 mA — four times the current. What happens to g_m?

Answer: B. g_m ∝ √I_D, so a 4× current buys a 2× transconductance. Watch the readout on the bench: dragging the current slider across its full range moves g_m across a much narrower range than it moved I_D.

The same bias point, two devices, two very different numbers

Take the FET this chapter is built around: V_TH = 2 V, k = 2 mA/V². Bias it at 5.72 mA — the exact current lesson 3’s bias circuit lands on — and V_OV works out to 1.598 V, so g_m = 2k V_OV ≈ 7.16 mA/V. Put a bipolar transistor at that same 5.72 mA and chapter 5’s formula gives g_m = I_C/V_T ≈ 221 mA/V. The bipolar transistor is roughly thirty times more transconductive, at the identical current.

Bias current	FET V_OV	FET g_m	BJT g_m (same I_C)	Ratio
1 mA	0.707 V	2.83 mA/V	38.7 mA/V	13.7×
2 mA	1.00 V	4.00 mA/V	77.3 mA/V	19.3×
4.5 mA	1.50 V	6.00 mA/V	174.0 mA/V	29.0×
10 mA	2.24 V	8.94 mA/V	386.6 mA/V	43.2×

The gap gets worse the harder you push, not better. A bipolar transistor's advantage over a FET at equal current grows with current, because g_m,FET ∝ √I_D while g_m,BJT ∝ I_C. This is the direct, unavoidable consequence of lesson 1’s parabola versus exponential — not a flaw in any particular part, but the shape of the physics itself.

So why use a FET at all? Zero gate current (lesson 1), a much wider linear window for the same reason, and — you will see in lesson 3 — a bias circuit that genuinely doesn’t care how weak you make it. Different trade, not a strictly better one.

In the wild

Why power MOSFETs run huge k values, not huge currents. To get useful g_m out of the square law without an enormous V_OV, manufacturers make k big — thousands of parallel channel fingers on one die. That is what “low R_DS(on), high g_fs” on a power MOSFET datasheet is buying.

Why a JFET input op-amp needs a second gain stage the bipolar version doesn’t. Lower g_m at the input, for the same bias current, means lower gain from that stage alone — made up for elsewhere in the chip.

The mA/V unit itself. It is not an accident that g_m is quoted in the same units for both device families. Whatever the shape of the law underneath, the small-signal model — a current source of value g_mv_gs — looks identical on paper. Only the number attached to it differs.

Before you move on

A FET's bias current is increased by a factor of nine. By what factor does g_m increase?

g_m ∝ √I_D, and √9 = 3. V_TH sets where the parabola starts, not the exponent on this relationship — it cancels out of the ratio entirely. This square-root scaling, not any specific number, is the one fact worth carrying out of this lesson.

Bench 02 · g_m against bias current, both families ACTIVE

● Locked until you commit a prediction above.

Drain current 1.0 mA

0.3 mA5 mA15 mA

V_OV—

FET g_m—

BJT g_m (same I)—

Ratio—

A divider that means exactly what it says

15 minutes · biasing with zero gate current

Recall From chapter 4: why did a bipolar bias divider need to be “stiff” — about ten times the base current? show answer

Chapter 4’s four-resistor bias earned its complexity honestly: the base draws current, that current is a fraction of whatever flows in the divider, and if the divider is too weak the base loads it and drags the voltage down — and β is back in your equations. The fix was to force ten times as much current through the divider as the base ever takes, so the loading becomes a rounding error.

A MOSFET's gate draws none of that current at all. So ask the question directly: what happens to the voltage at the midpoint of a resistor divider when the load on it is exactly zero?

Commit before you touch anything

A divider sets a MOSFET’s gate at 4.86 V. You then replace both divider resistors with ones one hundred times larger, keeping their ratio identical. What happens to the gate voltage, and to the bias current?

Answer: B. Watch the left-hand plot: dragging the divider-scale slider across two full decades leaves the trace dead flat. There is no base current here to load anything, so the divider can be made as weak as you like — limited only by how much standing current you’re willing to waste, never by accuracy.

Two knobs, and only one of them is a bias knob

With zero gate current, V_G = V_DD·R₂/(R₁+R₂), exactly, for any R₁ and R₂ at all. The bench’s divider — R₁ = 1 MΩ, R₂ = 680 kΩ — sets V_G = 4.857 V, full stop. That number does not know or care whether R₁ and R₂ are megohms or kilohms, only their ratio.

The genuine bias knob is the source resistor R_S, which still closes a real feedback loop: more drain current → more drop across R_S → less V_GS → less drain current pushing back. Solve I_D = k(V_G − I_DR_S − V_TH)² for I_D and you get a quadratic — not an exponential to iterate on the way chapter 2’s bias point needed, but genuine algebra with a closed-form root.

R_S	I_D	V_GS	V_OV	V_DS
100 Ω	8.62 mA	4.00 V	2.00 V	4.08 V
220 Ω	5.72 mA	3.60 V	1.60 V	6.05 V
400 Ω	3.89 mA	3.30 V	1.30 V	7.26 V

The loading rule from chapter 4 didn’t vanish — its input just went to zero. The rule was always “make the divider stiff compared with the current it has to supply.” A MOSFET gate demands zero current, and any divider is infinitely stiffer than that. The rule is satisfied automatically, not repealed.

There is a real cost to a very weak divider, just not an accuracy cost: R₁ at 100 MΩ makes the stage's input impedance enormous and its bias point rock solid — but it also makes the gate node sensitive to stray capacitance and noise pickup, and painfully slow to settle after power-on. Engineering trade-offs move; they rarely disappear.

In the wild

Why a FET input buffer can present a gigaohm to whatever it’s measuring. Chapter 3’s emitter follower already bought you a high input impedance; a MOSFET follower buys one that is, for practical purposes, limited only by the divider resistors you choose — not by any β.

Electrometers and pH probes. A pH probe's own output impedance can run into the hundreds of megohms. Only a FET input stage can pick up a usable signal from it without loading it into uselessness.

Why op-amp datasheets list “input bias current” separately for BJT and JFET input parts. A JFET-input op-amp, which you will meet properly in chapter 8, inherits exactly this property — its bias current is measured in picoamps, not the nanoamps to microamps typical of a bipolar input stage.

Before you move on

What sets a MOSFET common-source stage’s gate voltage, when biased with a resistor divider?

B describes the BJT rule from chapter 4, which does not transfer here because the thing it was protecting against — base current loading the divider — is zero for a MOSFET gate at DC. C is simply wrong; the divider is in fact the standard way to bias a MOSFET's gate.

Bench 03 · the divider that doesn't budge SATURATION

● Locked until you commit a prediction above.

Divider scale (R1:R2 ratio fixed) 1.0×

0.1×1×10×

Source resistor R_S 220 Ω

50 Ω270 Ω500 Ω

V_G—

I_D—

V_OV—

V_DS—

The common-source stage, and what it costs you

14 minutes · the same gain formula, a much smaller number

Recall From chapter 5: what is the voltage gain of a common-emitter stage, in terms of g_m? show answer

The small-signal model chapter 5 built — a controlled current source of value g_mv_in, driving whatever resistance sits at the output — does not care what physics set g_m. Swap a bipolar transistor for a MOSFET, ground the source the same way you grounded the emitter, and the gain formula carries over unchanged:

A_v = −g_m(R_D ∥ R_L)

Same shape as chapter 5’s −g_m(R_C∥R_L). The formula didn’t change. What changed is the number you plug in for g_m — and lesson 2 already told you that number is small.

Commit before you touch anything

Lesson 3’s stage is biased at 5.72 mA with R_D = 820 Ω, unloaded. A bipolar stage at the identical current and the identical collector resistor would give a gain around −180. Roughly what does this FET stage give?

Answer: B. −g_mR_D = −0.007164 × 820 ≈ −5.87. Lesson 2's thirty-fold gap in g_m shows up here directly, term for term, because R_D is the same 820 Ω in both cases.

Loading costs the same fraction it always did

Put a load on the drain and it competes with R_D for the current source's output current, exactly as R_L competed with R_C in chapter 5. The arithmetic is identical — parallel resistances shrink, gain shrinks with them — only the starting number is smaller.

Load R_L	R_D∥R_L	Gain
unloaded	820 Ω	−5.87
4.7 kΩ	698 Ω	−5.00
2.2 kΩ	597 Ω	−4.28
1.0 kΩ	451 Ω	−3.23

A single FET stage rarely stands alone for this exact reason. Where one bipolar common-emitter stage can deliver most of the gain a small circuit needs, a MOSFET stage this lightly biased typically needs two or three in a row, or a much larger R_D, or a much higher bias current — and lesson 2 already showed that last option runs into diminishing returns.

One route back: push R_D up instead of I_D. Gain is g_mR_D, and R_D is free to grow as long as the DC drop across it still leaves room for the drain to sit above V_G−V_TH — the saturation condition from lesson 1. That headroom trade is exactly chapter 4’s territory, replayed with a different device.

In the wild

Why op-amp front ends use a differential FET pair, not a single stage. Low individual g_m is compensated by using the FET pair purely for its low bias current and high input impedance, then handing the gain job to bipolar stages further in — each device family doing the job it is actually good at.

Source-follower buffers. Just as chapter 3’s emitter follower traded gain for impedance, a source follower does the same trick with an even lower starting g_m — and it is exactly the reason a source follower's output impedance (≈1/g_m) tends to run higher than an emitter follower's.

Why CMOS logic doesn’t care about any of this. A digital inverter only needs its FET to be a hard-on or hard-off switch, never a linear gain element — chapter 11 picks this up properly.

Before you move on

A common-source stage has g_m = 4 mA/V and R_D = 1.5 kΩ, unloaded. Gain?

−g_mR_D = −0.004 × 1500 = −6. Same formula as chapter 5, same units, and a reminder of how much smaller these numbers run once g_m is a FET's rather than a BJT's.

Bench 04 · gain against load ACTIVE

● Locked until you commit a prediction above.

Load resistor R_L unloaded

820 Ω4.7 kΩunloaded

FET gain—

Equivalent BJT gain—

R_D∥R_L—

A ceiling that moves — the wrong way

15 minutes · channel-length modulation, and the price of overdrive

Recall From chapter 5: what set the intrinsic gain ceiling g_mr_o of a bipolar stage, and did it depend on bias current? show answer

A real MOSFET's drain current climbs slightly as V_DS increases, even deep in saturation — the channel effectively shortens as the depletion region at the drain end grows, and current rises. The textbook fix is the same shape chapter 5 used for the Early effect:

I_D = k(V_GS−V_TH)²(1+λV_DS) r_o = 1/(λI_D)

λ plays V_A's role — a device parameter with units of inverse volts, sold on datasheets sometimes as λ directly and sometimes as its reciprocal, 1/λ, quoted in volts to look like an Early voltage. This bench uses λ = 0.02 V²⁻¹, so 1/λ = 50 V — in the same ballpark as chapter 5's V_A = 75 V.

Multiply g_m = 2k V_OV by r_o = 1/(λI_D), and since I_D = k V_OV², the k cancels:

g_mr_o = 2/(λV_OV)

Commit before you touch anything

Chapter 5's ceiling, g_mr_o = V_A/V_T, was fixed near 2900 no matter how the bipolar stage was biased. You bias this FET stage harder, raising V_OV. What happens to its ceiling?

Answer: C. g_mr_o = 2/(λV_OV) is inversely proportional to V_OV. Drag the bench's overdrive slider up and watch the ceiling readout fall, not rise. This is the flattest possible contradiction of chapter 5's fixed number, and it is real.

Why the two ceilings move in opposite directions

A BJT's V_A/V_T ceiling survives being bias-independent because both g_m and r_o scale with the same power of I_C — g_m up, r_o down, in exact proportion, at any current. A FET has no such cancellation on offer: g_m depends on V_OV to the first power, r_o also depends on V_OV — through I_D = k V_OV² — to the second power, and the mismatch is what leaves V_OV standing alone, in the denominator, once the algebra settles.

V_OV	0.4 V	0.8 V	1.2 V	1.6 V	2.0 V	3.0 V
g_mr_o	250	125	83	63	50	33

Lesson 1's wider linear window and lesson 5's shrinking ceiling are the same trade, seen twice. A larger V_OV buys you a wider small-signal window (lesson 1) and a smaller g_mr_o ceiling (this lesson) — you cannot have the wide window without paying the ceiling, and you cannot chase the ceiling without narrowing the window. The bipolar transistor never offers this choice; V_T is fixed by temperature either way.

In the wild

Why analog IC designers bias MOSFETs at a low overdrive — “weak” or “moderate” inversion — on purpose. A smaller V_OV costs linear range but buys gain, and in a differential pair buried inside a chip, gain usually wins the trade.

Why op-amp open-loop gain specs sometimes still surprise engineers who grew up on bipolar parts. A CMOS op-amp's per-stage gain ceiling depends on how each internal MOSFET is biased, not on a single fixed constant like V_A/V_T — which is part of why CMOS op-amps typically need more gain stages than bipolar ones for the same overall open-loop gain.

Short-channel devices, and why λ keeps climbing. Modern, physically tiny MOSFETs have proportionally larger λ — a shorter channel is more sensitive, percentage-wise, to the same drain depletion region — which is exactly why single-stage CMOS gain has gotten harder to find, not easier, as transistors have shrunk.

Before you move on

Why does a MOSFET's intrinsic gain ceiling fall as it is biased with more overdrive, while a BJT's does not?

λ itself is taken as a fixed device parameter here, same as V_A was for the BJT — A is not the mechanism. The real reason is the algebra: g_m∝V_OV and r_o∝1/V_OV², so their product still carries one power of V_OV in the denominator. The BJT's g_m∝I_C and r_o∝1/I_C cancel completely instead.

Bench 05 · the ceiling, against overdrive ACTIVE

● Locked until you commit a prediction above.

Overdrive voltage V_OV 1.60 V

0.3 V1.6 V3.0 V

g_m—

r_o—

g_mr_o — the ceiling—

BJT ceiling (fixed)—

Below the knee: a resistor you can dial in with a voltage

14 minutes · the triode region, and the FET as a switch

Recall From lesson 1: what condition on V_DS keeps a FET in the saturation region where the square law above applies? show answer

Every equation so far assumed V_DS ≥ V_OV — enough drain voltage that the channel pinches off at the drain end and current stops caring about V_DS at all, beyond λ's small correction. Bring V_DS down below V_OV and the channel stays open along its whole length instead. The device leaves the world of chapters 1–5 entirely and becomes something closer to a plain resistor:

I_D = k(2V_OVV_DS − V_DS²) for V_DS < V_OV

This is the triode region — an unfortunate name shared with vacuum tubes and meaning something different here, but it is what every textbook calls it. Near V_DS = 0 the V_DS² term is negligible and I_D ≈ 2k V_OV·V_DS — current proportional to voltage, which is exactly Ohm's law, with a resistance set by the gate voltage:

r_DS(on) = 1 / (2k V_OV)

Commit before you touch anything

You hold V_DS small and slide V_OV up, deep into triode. What happens to the drain–source resistance?

Answer: B. r_DS(on) = 1/(2k V_OV) falls as V_OV rises. Watch the curve's slope near the origin steepen as you drag the slider — a steeper line there is a lower resistance, the same reading you'd get from an ohmmeter across drain and source.

A resistor with a control pin

This is the property no bipolar transistor offers at all: a two-terminal element whose resistance is set by a third terminal that draws no current, works in either direction (swap drain and source in triode and nothing changes — the device is symmetric), and can go from megohms to a few ohms depending purely on a gate voltage.

V_OV	0.4 V	0.8 V	1.2 V	1.6 V	2.0 V
r_DS(on)	625 Ω	313 Ω	208 Ω	156 Ω	125 Ω

Two regions, two completely different jobs. Saturation, from lessons 1–5, is where a FET amplifies: a small gate voltage change makes a proportionally larger drain current change. Triode, this lesson, is where it switches or attenuates: a large gate voltage change turns a small resistance into a large one, or vice versa, with the drain and source behaving like the two ends of an ordinary two-terminal part. Confusing the two is a real, common bias-point mistake — and it is exactly what the V_DS ≥ V_OV check on this bench's badge is watching for.

In the wild

Analog multiplexers and audio mute circuits. A CMOS switch IC is a MOSFET (or a complementary pair of them) run deliberately in triode with the gate slammed between two rails — fully on or fully off, with r_DS(on) in the tens of ohms when on.

Voltage-controlled resistors in guitar pedals and synthesizers. Some vintage tremolo and compressor circuits bias a JFET in triode at an intermediate V_OV, using it as a resistor whose value a control voltage can sweep continuously — the entire circuit built on the linear relationship this lesson derived.

Why a MOSFET makes a better power switch than a bipolar transistor of similar size. A saturated BJT still drops V_CE(sat), typically a few hundred millivolts, no matter how hard you drive it. A MOSFET deep in triode can be driven to a genuine near-zero resistance, dropping only I×r_DS(on) — often millivolts — which is most of the reason modern switching power supplies are built from MOSFETs, not transistors.

Before you move on

What is the essential difference between a FET operating in saturation and one operating in triode?

Gate current is zero in both regions — B is never true for a MOSFET at DC. The real distinction, and the one that decides which job the device can do, is exactly A's: whether the drain current has pinched off against V_DS or is still tracking it.

Bench 06 · the full I–V curve, one V_GS at a time SATURATION

● Locked until you commit a prediction above.

Overdrive V_OV 1.60 V

0.3 V1.2 V2.0 V

Operating point V_DS 0.20 V

0 V2.5 V5 V

I_D at this point—

Local r_DS—

✓

Chapter checkpoint

8 minutes · six questions, and two of them reach back

Question 1

At DC, how much current flows into a MOSFET's gate lead?

The gate is insulated from the channel; nothing crosses at DC beyond immeasurable insulator leakage. This single fact is what makes the divider in lesson 3 exact rather than approximate.

Question 2

A FET's bias current is quadrupled. By what factor does g_m change?

g_m ∝ √I_D, so √4 = 2. A would be the bipolar answer — g_m ∝ I_C there — which is exactly the trap this chapter is built around.

Question 3

Reaching back to chapter 4: why did a BJT's bias divider need to carry about ten times the base current?

A stiff divider swamps the base current's loading effect so the bias point stops depending on the unpredictable, temperature-sensitive β. A MOSFET's gate current is exactly zero, so this loading problem — and the stiffness rule built to solve it — simply doesn't arise.

Question 4

A common-source stage has g_m = 5 mA/V, R_D = 2 kΩ, loaded by R_L = 2 kΩ. Gain?

R_D∥R_L = 1 kΩ, so −g_m(R_D∥R_L) = −0.005×1000 = −5. Same load-sharing arithmetic as chapter 5, working on a smaller g_m.

Question 5

You bias a FET harder, raising V_OV. What happens to its intrinsic gain ceiling g_mr_o?

This is lesson 5's sharpest result and the opposite of a BJT's behaviour: g_m and r_o don't cancel for a FET the way they do for a BJT, and the leftover V_OV sits in the denominator.

Question 6

Reaching back to chapter 5: what set the bipolar transistor's fixed g_mr_o ceiling near 2900, independent of bias current?

Neither β nor R_C appears in g_mr_o at all. It is this exact cancellation — absent for the FET, as lesson 5 showed — that makes the bipolar ceiling a constant of the device rather than a function of how you bias it.

Checkpoint score

0 / 6

Answer all six. Four or more and the chapter has landed.

Every word this chapter introduced

Gate L1

The control terminal, insulated from the channel. Draws zero current at DC.

Threshold voltage V_TH L1

The V_GS below which no channel exists and I_D = 0.

Square law L1

I_D = k(V_GS−V_TH)². The FET's transfer characteristic, a parabola rather than an exponential.

Overdrive voltage V_OV L1

V_GS−V_TH. A design choice, not a temperature-set constant like V_T.

Transconductance g_m L2

2k V_OV = 2√(k I_D). Grows with the square root of bias current, not in proportion to it.

Gate bias divider L3

Sets V_G = V_DDR₂/(R₁+R₂) exactly, for any divider strength, because the gate loads it with zero current.

Self-bias resistor R_S L3

The genuine bias-setting element in a divider-biased FET stage; closes a negative feedback loop through V_GS.

Common-source gain L4

−g_m(R_D∥R_L). Same shape as the BJT's common-emitter gain, built on a smaller g_m.

Channel-length modulation, λ L5

The FET's analogue of the Early effect. r_o = 1/(λI_D).

Intrinsic gain ceiling L5

g_mr_o = 2/(λV_OV) for a FET — unlike the BJT's fixed V_A/V_T, it falls as you bias the device harder.

Saturation region L5

V_DS ≥ V_OV. Where the square law and this chapter's amplifier equations apply.

Triode region L6

V_DS < V_OV. I_D depends on V_DS nearly linearly; the device behaves like a voltage-controlled resistor.

r_DS(on) L6

1/(2k V_OV). The channel's resistance deep in triode, near V_DS = 0.

Where this goes next

CH 08

The Op-Amp Bench

Several gain stages with a loop around them, sold as a black box — sometimes built from exactly the FET input stage this chapter's “in the wild” notes kept mentioning.

CH 09

The Mirror Bench

Current mirrors and active loads — where the fixed BJT ceiling and the moving FET ceiling both reappear as design constraints, this time inside a chip.

CH 10

The Difference Bench

The long-tailed pair and CMRR, built from two matched transistors of either family.

CH 11–12

CMOS and the Loop Bench

The digital inverter, and the feedback and stability ideas that hold every op-amp in chapter 8 together.

About the simulations. This chapter's device model is a square-law MOSFET, I_D = k(V_GS−V_TH)²(1+λV_DS) in saturation and I_D = k(2V_OVV_DS−V_DS²)(1+λV_DS) in triode, continuous across the V_DS = V_OV boundary by construction. Because the gate draws no current, bias points are solved directly from the exact divider voltage rather than iterated the way chapter 2's Ebers–Moll equations had to be — a damped fixed-point iteration is still used to fold λ's feedback through V_DS back into I_D wherever R_S or R_D is nonzero. Three simplifications worth knowing: k, V_TH and λ are held constant with temperature, all capacitors are ideal, and body effect (a threshold shift with source-to-body voltage, irrelevant on the grounded-source stages built here) is not modelled. The BJT comparison figures throughout reuse chapter 5's g_m = I_C/V_T and V_A = 75 V at the same operating current, so the ratios shown are genuine, not illustrative rounding. One figure worth flagging directly: bench 1's “theory” readout is the bare-device v̂/4V_OV formula, but its “measured” readout comes from resolving the whole circuit, including r_o (lesson 5) loading against R_D — so the two numbers sit a consistent few percent apart at every amplitude, not just at large signal. That gap is r_o, not an error; chapter 5's equivalent bench didn't show it only because its R_C was small next to its much larger r_o.